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GET /api/1.1/patches/2223635/?format=api
{ "id": 2223635, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-6-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260415202027.83008-6-philmd@linaro.org>", "date": "2026-04-15T20:20:25", "name": "[RFC,v5,5/6] target/mips: Convert MSA LD/ST.D (Doubleword Vector)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e8e4f27bd4746f73aea0b5b7e4c8ef81a37dc71e", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-6-philmd@linaro.org/mbox/", "series": [ { "id": 500037, "url": "http://patchwork.ozlabs.org/api/1.1/series/500037/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500037", "date": "2026-04-15T20:20:20", "name": "target/mips: Translate MSA vector load/store opcodes", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500037/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223635/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223635/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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with SMTP id\n 5b1f17b1804b1-488d687bf61mr317200555e9.25.1776284469049;\n Wed, 15 Apr 2026 13:21:09 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "To": "qemu-devel@nongnu.org,\n\tRichard Henderson <richard.henderson@linaro.org>", "Cc": "Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>", "Subject": "[RFC PATCH v5 5/6] target/mips: Convert MSA LD/ST.D (Doubleword\n Vector)", "Date": "Wed, 15 Apr 2026 22:20:25 +0200", "Message-ID": "<20260415202027.83008-6-philmd@linaro.org>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260415202027.83008-1-philmd@linaro.org>", "References": "<20260415202027.83008-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::331;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Replace runtime helpers by translation.\n\nReplace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st()\nwhich allow to respect atomicity.\n\nRemove the ensure_writable_pages() hack and MSALDST_PROTO macro.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/msa_helper.h.inc | 6 ----\n target/mips/tcg/msa_helper.c | 53 --------------------------------\n target/mips/tcg/msa_translate.c | 18 +----------\n 3 files changed, 1 insertion(+), 76 deletions(-)", "diff": "diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\nindex f0d31ceef29..e994353056f 100644\n--- a/target/mips/tcg/msa_helper.h.inc\n+++ b/target/mips/tcg/msa_helper.h.inc\n@@ -432,9 +432,3 @@ DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n-\n-#define MSALDST_PROTO(type) \\\n-DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n-DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n-MSALDST_PROTO(d)\n-#undef MSALDST_PROTO\ndiff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\nindex c93c0cddebc..67ec19ea95c 100644\n--- a/target/mips/tcg/msa_helper.c\n+++ b/target/mips/tcg/msa_helper.c\n@@ -21,11 +21,8 @@\n #include \"cpu.h\"\n #include \"internal.h\"\n #include \"tcg/tcg.h\"\n-#include \"accel/tcg/cpu-ldst.h\"\n-#include \"accel/tcg/probe.h\"\n #include \"exec/helper-proto.h\"\n #include \"exec/memop.h\"\n-#include \"exec/target_page.h\"\n #include \"fpu/softfloat.h\"\n #include \"fpu_helper.h\"\n \n@@ -8205,53 +8202,3 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,\n \n msa_move_v(pwd, pwx);\n }\n-\n-/* Data format min and max values */\n-#define DF_BITS(df) (1 << ((df) + 3))\n-\n-/* Element-by-element access macros */\n-#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))\n-\n-void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- d0 = cpu_ldq_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_data_ra(env, addr + 8, ra);\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n-#define MSA_PAGESPAN(x) \\\n- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)\n-\n-static inline void ensure_writable_pages(CPUMIPSState *env,\n- target_ulong addr,\n- int mmu_idx,\n- uintptr_t retaddr)\n-{\n- /* FIXME: Probe the actual accesses (pass and use a size) */\n- if (unlikely(MSA_PAGESPAN(addr))) {\n- /* first page */\n- probe_write(env, addr, 0, mmu_idx, retaddr);\n- /* second page */\n- addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n- probe_write(env, addr, 0, mmu_idx, retaddr);\n- }\n-}\n-\n-void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n-\n- ensure_writable_pages(env, addr, mmu_idx, GETPC());\n-\n- cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra);\n- cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra);\n-}\ndiff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 8486508f5ba..b1d764bd179 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -785,8 +785,8 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n MO_ATOM_NONE,\n MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n+ MO_ATOM_IFALIGN_PAIR\n };\n- TCGv_i32 wd;\n TCGv_i128 t16;\n TCGv_va addr;\n MemOp mop;\n@@ -801,22 +801,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n addr = tcgv_va_temp_new();\n gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df);\n \n- wd = tcg_constant_i32(a->wd);\n-\n- if (is_load) {\n- switch (a->df) {\n- case 3:\n- gen_helper_msa_ld_d(tcg_env, wd, addr);\n- return true;\n- }\n- } else {\n- switch (a->df) {\n- case 3:\n- gen_helper_msa_st_d(tcg_env, wd, addr);\n- return true;\n- }\n- }\n-\n t16 = tcg_temp_new_i128();\n \n mop = MO_128 | MO_LE;\n", "prefixes": [ "RFC", "v5", "5/6" ] }