[{"id":3677878,"web_url":"http://patchwork.ozlabs.org/comment/3677878/","msgid":"","list_archive_url":null,"date":"2026-04-16T00:18:11","subject":"Re: [RFC PATCH v5 5/6] target/mips: Convert MSA LD/ST.D (Doubleword\n Vector)","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/16/26 06:20, Philippe Mathieu-Daudé wrote:\n> Replace runtime helpers by translation.\n> \n> Replace the legacy cpu_ld/st*_data_ra() calls by tcg_gen_qemu_ld/st()\n> which allow to respect atomicity.\n> \n> Remove the ensure_writable_pages() hack and MSALDST_PROTO macro.\n> \n> Signed-off-by: Philippe Mathieu-Daudé \n> ---\n> target/mips/tcg/msa_helper.h.inc | 6 ----\n> target/mips/tcg/msa_helper.c | 53 --------------------------------\n> target/mips/tcg/msa_translate.c | 18 +----------\n> 3 files changed, 1 insertion(+), 76 deletions(-)\n> \n> diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\n> index f0d31ceef29..e994353056f 100644\n> --- a/target/mips/tcg/msa_helper.h.inc\n> +++ b/target/mips/tcg/msa_helper.h.inc\n> @@ -432,9 +432,3 @@ DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)\n> DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)\n> DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)\n> DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n> -\n> -#define MSALDST_PROTO(type) \\\n> -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n> -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n> -MSALDST_PROTO(d)\n> -#undef MSALDST_PROTO\n> diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\n> index c93c0cddebc..67ec19ea95c 100644\n> --- a/target/mips/tcg/msa_helper.c\n> +++ b/target/mips/tcg/msa_helper.c\n> @@ -21,11 +21,8 @@\n> #include \"cpu.h\"\n> #include \"internal.h\"\n> #include \"tcg/tcg.h\"\n> -#include \"accel/tcg/cpu-ldst.h\"\n> -#include \"accel/tcg/probe.h\"\n> #include \"exec/helper-proto.h\"\n> #include \"exec/memop.h\"\n> -#include \"exec/target_page.h\"\n> #include \"fpu/softfloat.h\"\n> #include \"fpu_helper.h\"\n> \n> @@ -8205,53 +8202,3 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,\n> \n> msa_move_v(pwd, pwx);\n> }\n> -\n> -/* Data format min and max values */\n> -#define DF_BITS(df) (1 << ((df) + 3))\n> -\n> -/* Element-by-element access macros */\n> -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))\n> -\n> -void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,\n> - target_ulong addr)\n> -{\n> - wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n> - uintptr_t ra = GETPC();\n> - uint64_t d0, d1;\n> -\n> - d0 = cpu_ldq_data_ra(env, addr + 0, ra);\n> - d1 = cpu_ldq_data_ra(env, addr + 8, ra);\n> - pwd->d[0] = d0;\n> - pwd->d[1] = d1;\n> -}\n> -\n> -#define MSA_PAGESPAN(x) \\\n> - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)\n> -\n> -static inline void ensure_writable_pages(CPUMIPSState *env,\n> - target_ulong addr,\n> - int mmu_idx,\n> - uintptr_t retaddr)\n> -{\n> - /* FIXME: Probe the actual accesses (pass and use a size) */\n> - if (unlikely(MSA_PAGESPAN(addr))) {\n> - /* first page */\n> - probe_write(env, addr, 0, mmu_idx, retaddr);\n> - /* second page */\n> - addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n> - probe_write(env, addr, 0, mmu_idx, retaddr);\n> - }\n> -}\n> -\n> -void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,\n> - target_ulong addr)\n> -{\n> - wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n> - int mmu_idx = mips_env_mmu_index(env);\n> - uintptr_t ra = GETPC();\n> -\n> - ensure_writable_pages(env, addr, mmu_idx, GETPC());\n> -\n> - cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra);\n> - cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra);\n> -}\n\nThis isn't using a LE operation...\n\n> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\n> index 8486508f5ba..b1d764bd179 100644\n> --- a/target/mips/tcg/msa_translate.c\n> +++ b/target/mips/tcg/msa_translate.c\n> @@ -785,8 +785,8 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> MO_ATOM_NONE,\n> MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n> MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n> + MO_ATOM_IFALIGN_PAIR\n> };\n> - TCGv_i32 wd;\n> TCGv_i128 t16;\n> TCGv_va addr;\n> MemOp mop;\n> @@ -801,22 +801,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n> addr = tcgv_va_temp_new();\n> gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df);\n> \n> - wd = tcg_constant_i32(a->wd);\n> -\n> - if (is_load) {\n> - switch (a->df) {\n> - case 3:\n> - gen_helper_msa_ld_d(tcg_env, wd, addr);\n> - return true;\n> - }\n> - } else {\n> - switch (a->df) {\n> - case 3:\n> - gen_helper_msa_st_d(tcg_env, wd, addr);\n> - return true;\n> - }\n> - }\n> -\n> t16 = tcg_temp_new_i128();\n> \n> mop = MO_128 | MO_LE;\n\n... which you're now getting from here.\n\nYou could bswap d0 and d1, or you could have the 64-bit path reorder d0 and d1 in t16 and \nmop ^= MO_BSWAP.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CxH7fPS1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwzBg1b8lz1yG9\n\tfor ; Thu, 16 Apr 2026 10:18:35 +1000 (AEST)","from localhost ([::1] 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