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GET /api/1.1/patches/2223633/?format=api
{ "id": 2223633, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223633/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-4-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260415202027.83008-4-philmd@linaro.org>", "date": "2026-04-15T20:20:23", "name": "[RFC,v5,3/6] target/mips: Convert MSA LD/ST.H (Halfword Vector)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "66ff4cdc615f3076832cf50f2b16f3e0e7119038", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-4-philmd@linaro.org/mbox/", "series": [ { "id": 500037, "url": "http://patchwork.ozlabs.org/api/1.1/series/500037/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500037", "date": "2026-04-15T20:20:20", "name": "target/mips: Translate MSA vector load/store opcodes", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500037/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223633/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223633/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=By+R9G4I;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Replace runtime helpers by translation.\n\nReplace the legacy cpu_ld/st*_data_ra() calls by\ntcg_gen_qemu_ld/st() which allow to respect atomicity.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/msa_helper.h.inc | 1 -\n target/mips/tcg/msa_helper.c | 48 --------------------------------\n target/mips/tcg/msa_translate.c | 32 +++++++++++++++++----\n 3 files changed, 26 insertions(+), 55 deletions(-)", "diff": "diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\nindex 50a2732e916..86a79bf804c 100644\n--- a/target/mips/tcg/msa_helper.h.inc\n+++ b/target/mips/tcg/msa_helper.h.inc\n@@ -436,7 +436,6 @@ DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n #define MSALDST_PROTO(type) \\\n DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n-MSALDST_PROTO(h)\n MSALDST_PROTO(w)\n MSALDST_PROTO(d)\n #undef MSALDST_PROTO\ndiff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\nindex d9f35fca657..5489d8830dd 100644\n--- a/target/mips/tcg/msa_helper.c\n+++ b/target/mips/tcg/msa_helper.c\n@@ -8212,38 +8212,11 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,\n /* Element-by-element access macros */\n #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))\n \n-static inline uint64_t bswap16x4(uint64_t x)\n-{\n- uint64_t m = 0x00ff00ff00ff00ffull;\n- return ((x & m) << 8) | ((x >> 8) & m);\n-}\n-\n static inline uint64_t bswap32x2(uint64_t x)\n {\n return ror64(bswap64(x), 32);\n }\n \n-void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- /*\n- * Load 8 bytes at a time. Use little-endian load, then for\n- * big-endian target, we must then swap the four halfwords.\n- */\n- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap16x4(d0);\n- d1 = bswap16x4(d1);\n- }\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,\n target_ulong addr)\n {\n@@ -8296,27 +8269,6 @@ static inline void ensure_writable_pages(CPUMIPSState *env,\n }\n }\n \n-void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- ensure_writable_pages(env, addr, mmu_idx, ra);\n-\n- /* Store 8 bytes at a time. See helper_msa_ld_h. */\n- d0 = pwd->d[0];\n- d1 = pwd->d[1];\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap16x4(d0);\n- d1 = bswap16x4(d1);\n- }\n- cpu_stq_le_data_ra(env, addr + 0, d0, ra);\n- cpu_stq_le_data_ra(env, addr + 8, d1, ra);\n-}\n-\n void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,\n target_ulong addr)\n {\ndiff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 340a0a14aaf..111d9eedd11 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -754,10 +754,27 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);\n TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);\n TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);\n \n+/*\n+ * Byte pattern: ab.cd.ef.gh -> ba.dc.fe.bg\n+ */\n+static void gen_bswap16x4_i64(TCGv_i64 dst, TCGv_i64 src)\n+{\n+ uint64_t m = 0x00ff00ff00ff00ffull;\n+ TCGv_i64 t0 = tcg_temp_new_i64();\n+ TCGv_i64 t1 = tcg_temp_new_i64();\n+ /* src = abcdefgh */\n+ tcg_gen_andi_i64(t0, src, m); /* t0 = .b.d.f.h */\n+ tcg_gen_shli_i64(t0, t0, 8); /* t0 = b.d.f.h. */\n+ tcg_gen_shri_i64(t1, src, 8); /* t1 = habcdefg */\n+ tcg_gen_andi_i64(t1, t1, m); /* t1 = .a.c.e.g */\n+ tcg_gen_or_i64(dst, t0, t1); /* dst = badcfebg */\n+}\n+\n static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n {\n static const MemOp mo_atom_df[4] = {\n MO_ATOM_NONE,\n+ MO_ATOM_SUBALIGN, /* Slightly stronger than required */\n };\n TCGv_i32 wd;\n TCGv_i128 t16;\n@@ -778,9 +795,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n \n if (is_load) {\n switch (a->df) {\n- case 1:\n- gen_helper_msa_ld_h(tcg_env, wd, addr);\n- return true;\n case 2:\n gen_helper_msa_ld_w(tcg_env, wd, addr);\n return true;\n@@ -790,9 +804,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n }\n } else {\n switch (a->df) {\n- case 1:\n- gen_helper_msa_st_h(tcg_env, wd, addr);\n- return true;\n case 2:\n gen_helper_msa_st_w(tcg_env, wd, addr);\n return true;\n@@ -813,6 +824,15 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n tcg_gen_extr_i128_i64(d0, d1, t16);\n }\n \n+ if (mo_endian(ctx) != MO_LE) {\n+ switch (a->df) {\n+ case 1:\n+ gen_bswap16x4_i64(d0, d0);\n+ gen_bswap16x4_i64(d1, d1);\n+ break;\n+ }\n+ }\n+\n if (!is_load) {\n tcg_gen_concat_i64_i128(t16, d0, d1);\n tcg_gen_qemu_st_i128(t16, addr, ctx->mem_idx, mop);\n", "prefixes": [ "RFC", "v5", "3/6" ] }