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GET /api/1.1/patches/2223630/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2223630,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223630/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-2-philmd@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260415202027.83008-2-philmd@linaro.org>",
    "date": "2026-04-15T20:20:21",
    "name": "[RFC,v5,1/6] target/mips: Expand TRANS_DF_iv() macro for MSA Load/Store",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "925e6009e72aba6b0fe07a303aab37bf72151cd5",
    "submitter": {
        "id": 85046,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api",
        "name": "Philippe Mathieu-Daudé",
        "email": "philmd@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415202027.83008-2-philmd@linaro.org/mbox/",
    "series": [
        {
            "id": 500037,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/500037/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500037",
            "date": "2026-04-15T20:20:20",
            "name": "target/mips: Translate MSA vector load/store opcodes",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/500037/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2223630/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2223630/checks/",
    "tags": {},
    "headers": {
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        "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
        "To": "qemu-devel@nongnu.org,\n\tRichard Henderson <richard.henderson@linaro.org>",
        "Cc": "Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>",
        "Subject": "[RFC PATCH v5 1/6] target/mips: Expand TRANS_DF_iv() macro for MSA\n Load/Store",
        "Date": "Wed, 15 Apr 2026 22:20:21 +0200",
        "Message-ID": "<20260415202027.83008-2-philmd@linaro.org>",
        "X-Mailer": "git-send-email 2.53.0",
        "In-Reply-To": "<20260415202027.83008-1-philmd@linaro.org>",
        "References": "<20260415202027.83008-1-philmd@linaro.org>",
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        "Precedence": "list",
        "List-Id": "qemu development <qemu-devel.nongnu.org>",
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        "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"
    },
    "content": "In order to ease the conversion of MSA Load/Store runtime\nhelpers to translated code, expand the TRANS_DF_iv() macro.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/msa_translate.c | 59 ++++++++++++++++++++++++++-------\n 1 file changed, 47 insertions(+), 12 deletions(-)",
    "diff": "diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 82b149922fa..2e1a769e032 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -164,7 +164,6 @@ static inline bool check_msa_enabled(DisasContext *ctx)\n     return true;\n }\n \n-typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);\n typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32);\n typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);\n typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);\n@@ -175,9 +174,6 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);\n     }; \\\n     TRANS(NAME, trans_func, NAME##_tab[a->df])\n \n-#define TRANS_DF_iv(NAME, trans_func, gen_func) \\\n-    TRANS_DF_x(iv, NAME, trans_func, gen_func)\n-\n #define TRANS_DF_ii(NAME, trans_func, gen_func) \\\n     TRANS_DF_x(ii, NAME, trans_func, gen_func)\n \n@@ -758,25 +754,64 @@ TRANS(FTINT_U,  trans_msa_2rf, gen_helper_msa_ftint_u_df);\n TRANS(FFINT_S,  trans_msa_2rf, gen_helper_msa_ffint_s_df);\n TRANS(FFINT_U,  trans_msa_2rf, gen_helper_msa_ffint_u_df);\n \n-static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,\n-                           gen_helper_piv *gen_msa_ldst)\n+static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, bool is_load)\n {\n-    TCGv taddr;\n+    TCGv_i32 wd;\n+    TCGv_va addr;\n \n     if (!check_msa_enabled(ctx)) {\n         return true;\n     }\n \n-    taddr = tcg_temp_new();\n+    addr = tcgv_va_temp_new();\n+    gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df);\n \n-    gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);\n-    gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);\n+    wd = tcg_constant_i32(a->wd);\n+\n+    if (is_load) {\n+        switch (a->df) {\n+        case 0:\n+            gen_helper_msa_ld_b(tcg_env, wd, addr);\n+            return true;\n+        case 1:\n+            gen_helper_msa_ld_h(tcg_env, wd, addr);\n+            return true;\n+        case 2:\n+            gen_helper_msa_ld_w(tcg_env, wd, addr);\n+            return true;\n+        case 3:\n+            gen_helper_msa_ld_d(tcg_env, wd, addr);\n+            return true;\n+        }\n+    } else {\n+        switch (a->df) {\n+        case 0:\n+            gen_helper_msa_st_b(tcg_env, wd, addr);\n+            return true;\n+        case 1:\n+            gen_helper_msa_st_h(tcg_env, wd, addr);\n+            return true;\n+        case 2:\n+            gen_helper_msa_st_w(tcg_env, wd, addr);\n+            return true;\n+        case 3:\n+            gen_helper_msa_st_d(tcg_env, wd, addr);\n+            return true;\n+        }\n+    }\n \n     return true;\n }\n \n-TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld);\n-TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);\n+static bool trans_LD(DisasContext *ctx, arg_msa_i *a)\n+{\n+    return trans_msa_ldst(ctx, a, true);\n+}\n+\n+static bool trans_ST(DisasContext *ctx, arg_msa_i *a)\n+{\n+    return trans_msa_ldst(ctx, a, false);\n+}\n \n static bool trans_LSA(DisasContext *ctx, arg_r *a)\n {\n",
    "prefixes": [
        "RFC",
        "v5",
        "1/6"
    ]
}