Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222717/?format=api
{ "id": 2222717, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com>", "date": "2026-04-13T14:05:30", "name": "[v3,07/21] drm/panel: himax-hx83102: support Waveshare 12.3\" DSI panel", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "734071b6a247642195aac5226ef72ca0b3579de2", "submitter": { "id": 90483, "url": "http://patchwork.ozlabs.org/api/1.1/people/90483/?format=api", "name": "Dmitry Baryshkov", "email": "dmitry.baryshkov@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com/mbox/", "series": [ { "id": 499710, "url": "http://patchwork.ozlabs.org/api/1.1/series/499710/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499710", "date": "2026-04-13T14:05:24", "name": "drm/panel: support Waveshare DSI TOUCH kits", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499710/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222717/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222717/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35102-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=efTQyhD5;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=PDTevl2H;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; helo=sto.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35102-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"efTQyhD5\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"PDTevl2H\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvTk85FK2z1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 14 Apr 2026 00:07:12 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id ACBBD301A760\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 13 Apr 2026 14:06:33 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E136D3CBE7F;\n\tMon, 13 Apr 2026 14:05:54 +0000 (UTC)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id F261D3D6CDD\n\tfor <linux-gpio@vger.kernel.org>; Mon, 13 Apr 2026 14:05:49 +0000 (UTC)", "from pps.filterd (m0279868.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63DCeuvr440447\n\tfor <linux-gpio@vger.kernel.org>; Mon, 13 Apr 2026 14:05:48 GMT", "from mail-oi1-f200.google.com (mail-oi1-f200.google.com\n [209.85.167.200])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dfevtnqt8-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-gpio@vger.kernel.org>; Mon, 13 Apr 2026 14:05:47 +0000 (GMT)", "by mail-oi1-f200.google.com with SMTP id\n 5614622812f47-467e00b684eso2791828b6e.3\n for <linux-gpio@vger.kernel.org>;\n Mon, 13 Apr 2026 07:05:47 -0700 (PDT)", "from umbar.lan\n (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi.\n [2001:14ba:a073:af00:264b:feff:fe8b:be8a])\n by smtp.gmail.com with ESMTPSA id\n 2adb3069b0e04-5a3eee8c91csm2687521e87.19.2026.04.13.07.05.44\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 13 Apr 2026 07:05:44 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776089154; cv=none;\n b=ezuDCBaoytPZFg6bPI4Q33+6lP80Rt36P/55YXX2Y1B8W0ebxhVtDHaHu81Jc/2Io9P6IqhyhBhEz9eGc82ChnKq5I5/seCu+8Ge01N7FIrT2sEUsvPR8Wbk3fc/RUDvAQPCGcwKjp7vwx/WXzOTHxIzPYAz3VHumVlJceqZ5yE=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776089154; c=relaxed/simple;\n\tbh=i3q+ZnanPV6G/1cXFp+xLd7TApeXEUOIHGf51LyJVuc=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=NFM7v9OFqTjO/ouj8t+ha6iYni1GNa5ZMwT35Zzc+m/Fpxj55/ly9nDxSVRTG4tNel/BQjM6om29xlXHfe40h+hW4q57u5B+Yk4iFJfZVdFz0Jye9L8dqZD1EovrYI2j8c7Gmz7lko6Fp7Et49CdeV4MjXVfj9Fdv8tTDj+ieXA=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=oss.qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=efTQyhD5;\n dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=PDTevl2H; arc=none smtp.client-ip=205.220.180.131", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n\tW391/07ZMOVK4atGULPN5+Bm76UZpkvj4qbP9sDT2Og=; b=efTQyhD5LC2sdgBu\n\tSRzcsRyKiLVWJomECs6EFn+jRUAjHayuImqelEGo2Si/t5ePLG2o391D7UU2HPal\n\tz57EcS7T6Jk6zEwOlX280BLvHtjreoLWIcDDynF/hac1alrbYVTonVBcZIMn+Axj\n\tHkbj1NkZIIN2V02LbdVFGp6B4dq7fYswTAd/a2R47yfprCxOFNi9XoGavTNueUtC\n\tTU0+52Y6y6ALL1Y1M9j+bUBJq40n5J9QfPH+8JwQ18EyYzFFnfZGJ95SIiy2L3Kl\n\tFA9rmv+h3KeQkMCSuc1rWFVCG6qYyF97iX5RxMJEG76RoIrDn8+LWH1RakHsWtWB\n\ttBEmVg==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1776089147; x=1776693947;\n darn=vger.kernel.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to;\n bh=W391/07ZMOVK4atGULPN5+Bm76UZpkvj4qbP9sDT2Og=;\n b=PDTevl2Hw3dBANXW6HOEBkNgEsqNdc5o2YeOsXSAoxtP0ArGXJZ95jnZxicaALLk64\n DF8ARz8tPRZbykvo5doH3wiPLUGvrRuKhsy6kGIEKFTPFyyIICq2RDsJ87Zqttxm0fJ3\n CK/68z5rg8k8cp4TTbKqvMGOGA26SoHsO5wL50esxEtvQGQhoBom7D87T8oymnkP+ayX\n CTjk1HaqcK7as3/QSAShKSC0Vc23fASVYcwFXy/VxGwYKWmawalid7jIIwy5Sb9jYk5j\n 6bFTbgl00hr7GR961bEPG5o/codhqd1wP7bN5s5sGvqriE32DoETAA+WKFJV3irLmIXR\n lUIg==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776089147; x=1776693947;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=W391/07ZMOVK4atGULPN5+Bm76UZpkvj4qbP9sDT2Og=;\n b=N3P8cupK8yn3lgSCo78xhm0gRJ5HdH3i37kJz5n4PNIXcotPQcarK4fDj/ssTR7FIL\n 0QSZcDcN+UeJMhtwuVFZhrSmNar2XnalOS9Hm0SLr44vKAgjGsWAGtcsJFpNT3w1c9Kd\n +jwfhGHsrHtqOvwRmcyKDhoZ1KZWnswLs+6e2IaZvCptKNVUTv2i/R8Uqp8VwSgEhUug\n 2VF0VY9OsRJTD00txQWWpY1YEyp16gHr0LGQa2QCjOywVlkU9CZBR/i0HQgO5ZArDjb3\n r6UAZjT9D1aOzyy0nCinhdgjZV7810uknmq8/N3z8X+k0Yq+HZi+HnDHl8hItLwD8pei\n hh1g==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ+yri7QL4y2BxI3oijjsXejj6uJMfnVggb3XiQBznKKbp0qdUaMh6Oeih2+WYRz79u0BR+frjDZrs0i@vger.kernel.org", "X-Gm-Message-State": "AOJu0Ywv43Ng/qdjkRzAHEHLNQbU+K7hWq749MpXE9Q01APUzw3WDoyd\n\t5/mm8nsOyIMYK8crm9kBMbPSVZgKWm3aQbATLF9MQ9MRtwJu0EMgro0fy7vLkbuMOEJKpOLf3dO\n\tLDr0AQNZPMMokXrSYiSb55+wTw6F+ZuoMABayPpIo61al59/4BBnS3oJPW8ng/ePa", "X-Gm-Gg": "AeBDiesICcNY2AZX3h6NiOWuaozmVoECGlXBZx6g2kusfHBfLe+dLdft2Im0R8pYQd+\n\tS3RW1y3Do0ZGPv6ZysjesZb584e7PlB/Ra50BvhAON7PEuIse64MKPDRj6LXODBtSMjZxEy7CGq\n\trSZSAC3gugxgUy4+5qysVJncH5gyH5w1tTNFu9i8yw03KhivpxJW3BbkmY6QuJup0Qkt0vTBrVL\n\twd5DQBKM9BLQeFV56yorNl/hRgk2oiyf7FFqUdjR53npqNMjMOMpKjWrP5FoVoGiQ/qOOW/KzNf\n\tpNjIJiuMnGmgqx5Rt/jBzjLTOO1DGT+fVPra/lNTCJ8uEkXkib5lLk+ZyNiMYEOhbB1LYO/Unvp\n\tT+o8cHSO+e5N8LFvwTXlWe323L3LhO8UVFsgQlfIawljiLA7w4KIHB1EvOVnoGCNJ9GoDoesu3+\n\tBl0ZOeLLuou/cuxZ/hECYRUMy4qRE7ZGl/0Zk=", "X-Received": [ "by 2002:a05:6808:c1b3:b0:466:fed2:54d4 with SMTP id\n 5614622812f47-4789c64b551mr6917546b6e.10.1776089146940;\n Mon, 13 Apr 2026 07:05:46 -0700 (PDT)", "by 2002:a05:6808:c1b3:b0:466:fed2:54d4 with SMTP id\n 5614622812f47-4789c64b551mr6917489b6e.10.1776089146306;\n Mon, 13 Apr 2026 07:05:46 -0700 (PDT)" ], "From": "Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>", "Date": "Mon, 13 Apr 2026 17:05:30 +0300", "Subject": "[PATCH v3 07/21] drm/panel: himax-hx83102: support Waveshare 12.3\"\n DSI panel", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com>", "References": "<20260413-waveshare-dsi-touch-v3-0-3aeb53022c32@oss.qualcomm.com>", "In-Reply-To": "<20260413-waveshare-dsi-touch-v3-0-3aeb53022c32@oss.qualcomm.com>", "To": "Neil Armstrong <neil.armstrong@linaro.org>,\n Jessica Zhang <jesszhan0024@gmail.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n Maxime Ripard <mripard@kernel.org>,\n Thomas Zimmermann <tzimmermann@suse.de>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Cong Yang <yangcong5@huaqin.corp-partner.google.com>,\n Ondrej Jirman <megi@xff.cz>,\n Javier Martinez Canillas <javierm@redhat.com>,\n Jagan Teki <jagan@edgeble.ai>, Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Bartosz Golaszewski <brgl@kernel.org>,\n Jie Gan <jie.gan@oss.qualcomm.com>", "Cc": "dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=8981;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=i3q+ZnanPV6G/1cXFp+xLd7TApeXEUOIHGf51LyJVuc=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp3Pgn6QcqRki1UArqfPglemsHM2V8f3Uegiz5m\n 4gkvBf9VfaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCadz4JwAKCRCLPIo+Aiko\n 1YIqB/9nRIK6DjqVncGwfuEj9cqBCkbiwpsfBWxWpKPXyt3IBdfo6FQvwTrR7UHL4FrduLZvOiD\n tg3suPkynEVn9Qym32atFpvalcbSiGq4uK49fAxGqdSR/Y5cXsIWFyE8tvAJhu//yX7JhTUrMOu\n c520Mngy+IKeSGuHI8Aa+eWzCZSBxxNFh7QQXefEP/g+TFVEzkJ7lu1gcimdKvYV0pbX2vZOUIy\n PYUNaF7JhGjvm2JrnA6SCA6LCScYJtPs+7hsChOSjMnWB/tAqIT3KduxcK092YgKej/APHCcDax\n LZGGe1g8yduo0T7onG1A5r6pBTVw+Vdw05zXcanUOYqwX7gc", "X-Developer-Key": "i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp;\n fpr=8F88381DD5C873E4AE487DA5199BF1243632046A", "X-Authority-Analysis": "v=2.4 cv=RYWgzVtv c=1 sm=1 tr=0 ts=69dcf83b cx=c_pps\n a=AKZTfHrQPB8q3CcvmcIuDA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8\n a=6dGl3bZOZdHCWiLLNVsA:9 a=QEXdDO2ut3YA:10 a=pF_qn-MSjDawc0seGVz6:22", "X-Proofpoint-GUID": "p9XQbT8VhzeRzYRSfMsgzXXTuJ7aSZx0", "X-Proofpoint-ORIG-GUID": "p9XQbT8VhzeRzYRSfMsgzXXTuJ7aSZx0", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDEzMDEzOCBTYWx0ZWRfXzO0r21HYUhfO\n H21tsldONE2CaYUiuxivEdFx3A+c9diE6oKW9i157j1HL32+jxp4+N7qmYXU56fwhUOMZ6d9+1x\n 94jLm6JGCOLQzQn4VISG7hPJeuL2dO0TxDYT+h5vBiUBVlX/WIDr+R94r/O1MHcAYnJJGbfJoEO\n zhcaeAuw6zbHKkxLvaat7p7k/RjNYYkzeU9ZKEyQhPXsu2SesdeysvTz1NRrz+AVaZu0XFSim01\n oXJCKxCK56VDRo3AVFgiZDRzkDVBEEGqTQN4dKk6fE0eT8SCFGuhtiCxfORUYXYcYyb44oU+USX\n 9l79HxP2d+/i8ZfGNkz10i/4q6cqEGIQdIWOzjLSYFXl28C43U4PtdP0phDZCpAgNo+uI3ooyBN\n W6WCbhTFM1SOoyWwCnheRedztF/GrxXugs6qDmUTytqfpQglV/tCAC7dKH4cqY+htk/xO5oqwSz\n 65ulh4wqOLP7QXGzSOQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-13_03,2026-04-13_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0\n clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0\n lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604130138" }, "content": "Add support for the Waveshare 12.3\" DSI TOUCH-A panel. According to the\nvendor driver, it uses different mode_flags, so let the panel\ndescriptions override driver-wide defaults.\n\nSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>\n---\n drivers/gpu/drm/panel/panel-himax-hx83102.c | 144 +++++++++++++++++++++++++++-\n 1 file changed, 142 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c\nindex 8b2a68ee851e..eab67893da86 100644\n--- a/drivers/gpu/drm/panel/panel-himax-hx83102.c\n+++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c\n@@ -29,11 +29,14 @@\n #define HX83102_UNKNOWN_B8\t0xb8\n #define HX83102_SETEXTC\t\t0xb9\n #define HX83102_SETMIPI\t\t0xba\n+#define HX83102_UNKNOWN_BB\t0xbb\n #define HX83102_SETVDC\t\t0xbc\n #define HX83102_SETBANK\t\t0xbd\n #define HX83102_UNKNOWN_BE\t0xbe\n #define HX83102_SETPTBA\t\t0xbf\n #define HX83102_SETSTBA\t\t0xc0\n+#define HX83102_UNKNOWN_C2\t0xc2\n+#define HX83102_UNKNOWN_C6\t0xc6\n #define HX83102_SETTCON\t\t0xc7\n #define HX83102_SETRAMDMY\t0xc8\n #define HX83102_SETPWM\t\t0xc9\n@@ -78,6 +81,7 @@ struct hx83102_panel_desc {\n \t} size;\n \n \tbool has_backlight;\n+\tunsigned long mode_flags;\n \n \tint (*init)(struct hx83102 *ctx);\n };\n@@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)\n \treturn dsi_ctx.accum_err;\n }\n \n+/* This is HX83102-E, assuming commands are the same as the normal HX83102 */\n+static int waveshare_12_3_a_init(struct hx83102 *ctx)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,\n+\t\t\t\t 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,\n+\t\t\t\t 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,\n+\t\t\t\t 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,\n+\t\t\t\t 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,\n+\t\t\t\t 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,\n+\t\t\t\t 0x01, 0x58, 0x00, 0xff, 0x00, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n+\t\t\t\t 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,\n+\t\t\t\t 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,\n+\t\t\t\t 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,\n+\t\t\t\t 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,\n+\t\t\t\t 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,\n+\t\t\t\t 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,\n+\t\t\t\t 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,\n+\t\t\t\t 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,\n+\t\t\t\t 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,\n+\t\t\t\t 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,\n+\t\t\t\t 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n+\t\t\t\t 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,\n+\t\t\t\t 0x01);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,\n+\t\t\t\t 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,\n+\t\t\t\t 0x08, 0x00, 0x63, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,\n+\t\t\t\t 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,\n+\t\t\t\t 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,\n+\t\t\t\t 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,\n+\t\t\t\t 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,\n+\t\t\t\t 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,\n+\t\t\t\t 0x98, 0x98, 0x98, 0x98);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,\n+\t\t\t\t 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,\n+\t\t\t\t 0x2a, 0xaa, 0xaa, 0xaa);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n+\t\t\t\t 0xaa, 0xaa);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xff, 0xff, 0xff, 0xff,\n+\t\t\t\t 0xff, 0xf0, 0xff, 0xff,\n+\t\t\t\t 0xff, 0xff, 0xff, 0xf0);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\n+\treturn dsi_ctx.accum_err;\n+};\n+\n static const struct drm_display_mode starry_mode = {\n \t.clock = 162680,\n \t.hdisplay = 1200,\n@@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {\n \t.init = holitech_htf065h045_init,\n };\n \n+static const struct drm_display_mode waveshare_12_3_a_mode = {\n+\t.clock = 95000,\n+\t.hdisplay = 720,\n+\t.hsync_start = 720 + 10,\n+\t.hsync_end = 720 + 10 + 10,\n+\t.htotal = 720 + 10 + 10 + 12,\n+\t.vdisplay = 1920,\n+\t.vsync_start = 1920 + 64,\n+\t.vsync_end = 1920 + 64 + 18,\n+\t.vtotal = 1920 + 64 + 18 + 4,\n+\t.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {\n+\t.modes = &waveshare_12_3_a_mode,\n+\t.size = {\n+\t\t.width_mm = 109,\n+\t\t.height_mm = 292,\n+\t},\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+\t.init = waveshare_12_3_a_init,\n+};\n+\n static int hx83102_enable(struct drm_panel *panel)\n {\n \tmsleep(130);\n@@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)\n \tdesc = of_device_get_match_data(&dsi->dev);\n \tdsi->lanes = 4;\n \tdsi->format = MIPI_DSI_FMT_RGB888;\n-\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n-\t\t\t\t\t MIPI_DSI_MODE_LPM;\n+\tif (desc->mode_flags)\n+\t\tdsi->mode_flags = desc->mode_flags;\n+\telse\n+\t\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO |\n+\t\t\tMIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n+\t\t\tMIPI_DSI_MODE_LPM;\n \tctx->desc = desc;\n \tctx->dsi = dsi;\n \tret = hx83102_panel_add(ctx);\n@@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {\n \t{ .compatible = \"holitech,htf065h045\",\n \t .data = &holitech_htf065h045_desc\n \t},\n+\t{ .compatible = \"waveshare,12.3-dsi-touch-a\",\n+\t .data = &waveshare_12_3_inch_a_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, hx83102_of_match);\n", "prefixes": [ "v3", "07/21" ] }