[{"id":3677183,"web_url":"http://patchwork.ozlabs.org/comment/3677183/","msgid":"","list_archive_url":null,"date":"2026-04-14T12:57:22","subject":"Re: [PATCH v3 07/21] drm/panel: himax-hx83102: support Waveshare\n 12.3\" DSI panel","submitter":{"id":84903,"url":"http://patchwork.ozlabs.org/api/people/84903/","name":"Neil Armstrong","email":"neil.armstrong@linaro.org"},"content":"On 4/13/26 16:05, Dmitry Baryshkov wrote:\n> Add support for the Waveshare 12.3\" DSI TOUCH-A panel. According to the\n> vendor driver, it uses different mode_flags, so let the panel\n> descriptions override driver-wide defaults.\n> \n> Signed-off-by: Dmitry Baryshkov \n> ---\n> drivers/gpu/drm/panel/panel-himax-hx83102.c | 144 +++++++++++++++++++++++++++-\n> 1 file changed, 142 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c\n> index 8b2a68ee851e..eab67893da86 100644\n> --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c\n> +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c\n> @@ -29,11 +29,14 @@\n> #define HX83102_UNKNOWN_B8\t0xb8\n> #define HX83102_SETEXTC\t\t0xb9\n> #define HX83102_SETMIPI\t\t0xba\n> +#define HX83102_UNKNOWN_BB\t0xbb\n> #define HX83102_SETVDC\t\t0xbc\n> #define HX83102_SETBANK\t\t0xbd\n> #define HX83102_UNKNOWN_BE\t0xbe\n> #define HX83102_SETPTBA\t\t0xbf\n> #define HX83102_SETSTBA\t\t0xc0\n> +#define HX83102_UNKNOWN_C2\t0xc2\n> +#define HX83102_UNKNOWN_C6\t0xc6\n> #define HX83102_SETTCON\t\t0xc7\n> #define HX83102_SETRAMDMY\t0xc8\n> #define HX83102_SETPWM\t\t0xc9\n> @@ -78,6 +81,7 @@ struct hx83102_panel_desc {\n> \t} size;\n> \n> \tbool has_backlight;\n> +\tunsigned long mode_flags;\n> \n> \tint (*init)(struct hx83102 *ctx);\n> };\n> @@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)\n> \treturn dsi_ctx.accum_err;\n> }\n> \n> +/* This is HX83102-E, assuming commands are the same as the normal HX83102 */\n> +static int waveshare_12_3_a_init(struct hx83102 *ctx)\n> +{\n> +\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,\n> +\t\t\t\t 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,\n> +\t\t\t\t 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,\n> +\t\t\t\t 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,\n> +\t\t\t\t 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,\n> +\t\t\t\t 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,\n> +\t\t\t\t 0x01, 0x58, 0x00, 0xff, 0x00, 0xff);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n> +\t\t\t\t 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,\n> +\t\t\t\t 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,\n> +\t\t\t\t 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,\n> +\t\t\t\t 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,\n> +\t\t\t\t 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,\n> +\t\t\t\t 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,\n> +\t\t\t\t 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,\n> +\t\t\t\t 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,\n> +\t\t\t\t 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,\n> +\t\t\t\t 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,\n> +\t\t\t\t 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n> +\t\t\t\t 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,\n> +\t\t\t\t 0x01);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,\n> +\t\t\t\t 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,\n> +\t\t\t\t 0x08, 0x00, 0x63, 0x63);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,\n> +\t\t\t\t 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,\n> +\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,\n> +\t\t\t\t 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,\n> +\t\t\t\t 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,\n> +\t\t\t\t 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n> +\t\t\t\t 0x18, 0x18, 0x18, 0x18);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,\n> +\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,\n> +\t\t\t\t 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,\n> +\t\t\t\t 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,\n> +\t\t\t\t 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,\n> +\t\t\t\t 0x98, 0x98, 0x98, 0x98);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,\n> +\t\t\t\t 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n> +\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n> +\t\t\t\t 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,\n> +\t\t\t\t 0x2a, 0xaa, 0xaa, 0xaa);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n> +\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n> +\t\t\t\t 0xaa, 0xaa);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n> +\t\t\t\t 0xff, 0xff, 0xff, 0xff,\n> +\t\t\t\t 0xff, 0xf0, 0xff, 0xff,\n> +\t\t\t\t 0xff, 0xff, 0xff, 0xf0);\n> +\n> +\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n> +\n> +\treturn dsi_ctx.accum_err;\n> +};\n> +\n> static const struct drm_display_mode starry_mode = {\n> \t.clock = 162680,\n> \t.hdisplay = 1200,\n> @@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {\n> \t.init = holitech_htf065h045_init,\n> };\n> \n> +static const struct drm_display_mode waveshare_12_3_a_mode = {\n> +\t.clock = 95000,\n> +\t.hdisplay = 720,\n> +\t.hsync_start = 720 + 10,\n> +\t.hsync_end = 720 + 10 + 10,\n> +\t.htotal = 720 + 10 + 10 + 12,\n> +\t.vdisplay = 1920,\n> +\t.vsync_start = 1920 + 64,\n> +\t.vsync_end = 1920 + 64 + 18,\n> +\t.vtotal = 1920 + 64 + 18 + 4,\n> +\t.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n> +};\n> +\n> +static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {\n> +\t.modes = &waveshare_12_3_a_mode,\n> +\t.size = {\n> +\t\t.width_mm = 109,\n> +\t\t.height_mm = 292,\n> +\t},\n> +\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n> +\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n> +\t.init = waveshare_12_3_a_init,\n> +};\n> +\n> static int hx83102_enable(struct drm_panel *panel)\n> {\n> \tmsleep(130);\n> @@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)\n> \tdesc = of_device_get_match_data(&dsi->dev);\n> \tdsi->lanes = 4;\n> \tdsi->format = MIPI_DSI_FMT_RGB888;\n> -\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n> -\t\t\t\t\t MIPI_DSI_MODE_LPM;\n> +\tif (desc->mode_flags)\n> +\t\tdsi->mode_flags = desc->mode_flags;\n> +\telse\n> +\t\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO |\n> +\t\t\tMIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n> +\t\t\tMIPI_DSI_MODE_LPM;\n> \tctx->desc = desc;\n> \tctx->dsi = dsi;\n> \tret = hx83102_panel_add(ctx);\n> @@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {\n> \t{ .compatible = \"holitech,htf065h045\",\n> \t .data = &holitech_htf065h045_desc\n> \t},\n> +\t{ .compatible = \"waveshare,12.3-dsi-touch-a\",\n> +\t .data = &waveshare_12_3_inch_a_desc\n> +\t},\n> \t{ /* sentinel */ }\n> };\n> MODULE_DEVICE_TABLE(of, hx83102_of_match);\n> \n\nReviewed-by: Neil Armstrong \n\nThanks,\nNeil","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=oqhHOkfC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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(PDT)","Message-ID":"","Date":"Tue, 14 Apr 2026 14:57:22 +0200","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","From":"Neil Armstrong ","Reply-To":"Neil Armstrong ","Subject":"Re: [PATCH v3 07/21] drm/panel: himax-hx83102: support Waveshare\n 12.3\" DSI panel","To":"Dmitry Baryshkov ,\n Jessica Zhang , David Airlie ,\n Simona Vetter ,\n Maarten Lankhorst ,\n Maxime Ripard , Thomas Zimmermann ,\n Rob Herring , Krzysztof Kozlowski ,\n Conor Dooley ,\n Cong Yang ,\n Ondrej Jirman , Javier Martinez Canillas ,\n Jagan Teki , Liam Girdwood ,\n Mark Brown , Linus Walleij ,\n Bartosz Golaszewski , Jie Gan ","Cc":"dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org","References":"<20260413-waveshare-dsi-touch-v3-0-3aeb53022c32@oss.qualcomm.com>\n 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