Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222279/?format=api
{ "id": 2222279, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222279/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-7-james.hilliard1@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260411070637.72421-7-james.hilliard1@gmail.com>", "date": "2026-04-11T07:06:33", "name": "[7/9] target/mips: add Octeon ZUC crypto support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "de7dc7fe15100bd4afe307b023254cc923426a12", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.1/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-7-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 499531, "url": "http://patchwork.ozlabs.org/api/1.1/series/499531/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499531", "date": "2026-04-11T07:06:33", "name": "[1/9] linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499531/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222279/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222279/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=n0JL1iZ+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ft4W93bj8z1yH2\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 11 Apr 2026 17:07:47 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wBSQw-0001bT-1C; Sat, 11 Apr 2026 03:07:10 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wBSQv-0001bL-CC\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 03:07:09 -0400", "from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wBSQt-00010m-4M\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 03:07:09 -0400", "by mail-oi1-x235.google.com with SMTP id\n 5614622812f47-470145d7df5so1838941b6e.0\n for <qemu-devel@nongnu.org>; Sat, 11 Apr 2026 00:07:06 -0700 (PDT)", "from Mac.localdomain (71-218-253-186.hlrn.qwest.net.\n [71.218.253.186]) by smtp.gmail.com with ESMTPSA id\n 5614622812f47-478a0f1e841sm2651091b6e.5.2026.04.11.00.07.03\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Sat, 11 Apr 2026 00:07:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1775891226; x=1776496026; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=C5Hb/Kbp3EbT7B/m+Bd9c1VL9NV7LguO7HwGtzLx5RI=;\n b=n0JL1iZ+B9pMqd88l2ZHusAqPekaQyUhxgKDdWbS2aEZBeZtOudUef/it3ygfmSYbK\n d4GAk76ENMAoMQTD5CBdYxiY69TRrKwW2hDc0p+Ua4V9oNgSxfz69T20cbLwR6KHwzdI\n Evedyv36mX6iWLRfe7WWc+rqt/Qibpf229F17kNQbVeTyemNPUY7eUedw2+tPhBmJDTU\n K1nFEEfiQJALh8ipq4I8b8z1Is3D0bXUXN03L9mpJkL97mXNZyMrxoGg/JwBNFjtmCxM\n ML6+TqA/we+kMQswM460Xt9c5aEz/H8ovQIM0T6q3h5NvD4cKTjU13XhAheUdAHFV+QS\n YGAQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775891226; x=1776496026;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=C5Hb/Kbp3EbT7B/m+Bd9c1VL9NV7LguO7HwGtzLx5RI=;\n b=FR+hXXqMgBit66kr44pDzmsFMMTgkfBviLyTOcL//gsvt53Gdk8KlRbTset/JABceM\n 8Y8D58u+uasx7hFmV9NeAj+uAr1ATQihVQ2xK8njERbiu1rd12X/ZLAvCPzMyIj8dj06\n iGHByBgr26LdwODwsD0BMsHGdckc7Ya6OLmmjg1CRL+Q7iBJr7/dvhb/ggFJrz89WpYk\n /NL7UvbK+ks9BtSbrUWjUpwJxsJJ/xCmpDnHZN+VCP6INVS61Q8d1iUVYT4gZ/lCbgB1\n ydPOeJpLmFJB40dWuTG10zcjdJrLcb6Jgu9MTNBWQThp1vP8Foj0FFNox91uXd6CkI4B\n nWLQ==", "X-Gm-Message-State": "AOJu0YwBvmOD5UvCqdlZ8+lqwFAWVFOkmmuM65ofg8e+ZVdEBmJyKJq2\n uw+oqcQti+gj7IDoqpibWpEh0U1Rc4Im6h6PRrrocfBjbpJrVb8KRyPkmz29oHPW0cA=", "X-Gm-Gg": "AeBDiet4SyO9kjDrobcBueYKyHtAgfXnOf6qKtoZn3L9JVJPoQ8eOAyca4G26WeHu7Z\n Wgs9N9e0d2y6QN3cqFnRzSyNILE9RZbujOZnvoA6vVQZWoOsN09qUbgZInu9gUj+sOIMXwlOI3L\n XLuRMCB1R2D8iB0sUwDyOWfEVmEgJ6zShoLCNtbR5w0e1jKRBwk44u7K0c3/SRK4KBcKmnHtRXS\n pNWPjsOrumrJ79JPRDFsOwSNGVwRhTX5X/5EPyjkMQM+D3x/pIKdbO/J+lJ4SxFYHt2vy7Lrk6f\n QcSwlTSHQy58GauXCr8Q0UOQ0xPL36uqLUn29rlNPHVfgqx9BhMqQUsZvpPSTEV1TNjKrOkBgE7\n +SM7y8sN1rMyj9iw9j/TDcHKtBgaa7JY6nxDGrmiw2pIinRg9qVlOsTDKe8c0qei2kAijAw4VZk\n VMdNnXvJCjYlTprlVWqy8Ud2rLwHX+ACOffQAghosUbk5bk+4igIKbGw+WOJZTFtJ13+8qmc/rA\n cDlVs8/MafRdIc68QfrA3vh1/zvSJInelqg/8Az6rqUwQS8M5iTFt+xGvvjfV3rgNSvZE8=", "X-Received": "by 2002:a05:6808:c1b5:b0:467:2f84:b0c6 with SMTP id\n 5614622812f47-4789ca3aaa0mr3443597b6e.8.1775891225754;\n Sat, 11 Apr 2026 00:07:05 -0700 (PDT)", "From": "James Hilliard <james.hilliard1@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "James Hilliard <james.hilliard1@gmail.com>,\n Laurent Vivier <laurent@vivier.eu>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, =?utf-8?q?Philippe_Mathieu-?=\n\t=?utf-8?q?Daud=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>", "Subject": "[PATCH 7/9] target/mips: add Octeon ZUC crypto support", "Date": "Sat, 11 Apr 2026 01:06:33 -0600", "Message-ID": "<20260411070637.72421-7-james.hilliard1@gmail.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260411070637.72421-1-james.hilliard1@gmail.com>", "References": "<20260411070637.72421-1-james.hilliard1@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::235;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x235.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add the Octeon ZUC START and MORE selectors and model the shared state\nwindow used by the hardware interface.\n\nThis covers the keystream and MAC engine state, including the\nsave-and-restore view that overlaps the HSH/SHA3 bank.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n target/mips/cpu.h | 7 +\n target/mips/tcg/octeon_crypto.c | 323 ++++++++++++++++++++++++++++++++\n target/mips/tcg/translate.c | 2 +\n 3 files changed, 332 insertions(+)", "diff": "diff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex dc5223e165..8249b17e8a 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -541,6 +541,7 @@ typedef enum MIPSOcteonSharedMode {\n OCTEON_SHARED_MODE_NONE = 0,\n OCTEON_SHARED_MODE_SHA512,\n OCTEON_SHARED_MODE_SNOW3G,\n+ OCTEON_SHARED_MODE_ZUC,\n OCTEON_SHARED_MODE_SHA3,\n } MIPSOcteonSharedMode;\n \n@@ -704,6 +705,8 @@ typedef enum MIPSOcteonCop2Sel {\n OCTEON_COP2_SEL_SNOW3G_MORE = 0x404e,\n OCTEON_COP2_SEL_HSH_STARTSHA256 = 0x404f,\n OCTEON_COP2_SEL_SHA3_STARTOP = 0x4052,\n+ OCTEON_COP2_SEL_ZUC_START = 0x4055,\n+ OCTEON_COP2_SEL_ZUC_MORE = 0x4056,\n OCTEON_COP2_SEL_GFM_XORMUL1_REFLECT = 0x405d,\n OCTEON_COP2_SEL_HSH_STARTSHA1 = 0x4057,\n OCTEON_COP2_SEL_HSH_STARTSHA512 = 0x424f,\n@@ -738,6 +741,10 @@ typedef struct MIPSOcteonCryptoState {\n uint32_t snow3g_fsm[3];\n uint32_t snow3g_lfsr[16];\n uint64_t snow3g_result;\n+ uint32_t zuc_fsm[2];\n+ uint32_t zuc_lfsr[16];\n+ uint32_t zuc_window[3];\n+ uint32_t zuc_tresult;\n } MIPSOcteonCryptoState;\n \n typedef struct CPUArchState {\ndiff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c\nindex 7dde536560..317dd89cd2 100644\n--- a/target/mips/tcg/octeon_crypto.c\n+++ b/target/mips/tcg/octeon_crypto.c\n@@ -591,6 +591,251 @@ static int octeon_sha3_xordat_pos_from_sel(uint32_t sel)\n return -1;\n }\n \n+static const uint8_t octeon_zuc_s0[256] = {\n+ 0x3e, 0x72, 0x5b, 0x47, 0xca, 0xe0, 0x00, 0x33,\n+ 0x04, 0xd1, 0x54, 0x98, 0x09, 0xb9, 0x6d, 0xcb,\n+ 0x7b, 0x1b, 0xf9, 0x32, 0xaf, 0x9d, 0x6a, 0xa5,\n+ 0xb8, 0x2d, 0xfc, 0x1d, 0x08, 0x53, 0x03, 0x90,\n+ 0x4d, 0x4e, 0x84, 0x99, 0xe4, 0xce, 0xd9, 0x91,\n+ 0xdd, 0xb6, 0x85, 0x48, 0x8b, 0x29, 0x6e, 0xac,\n+ 0xcd, 0xc1, 0xf8, 0x1e, 0x73, 0x43, 0x69, 0xc6,\n+ 0xb5, 0xbd, 0xfd, 0x39, 0x63, 0x20, 0xd4, 0x38,\n+ 0x76, 0x7d, 0xb2, 0xa7, 0xcf, 0xed, 0x57, 0xc5,\n+ 0xf3, 0x2c, 0xbb, 0x14, 0x21, 0x06, 0x55, 0x9b,\n+ 0xe3, 0xef, 0x5e, 0x31, 0x4f, 0x7f, 0x5a, 0xa4,\n+ 0x0d, 0x82, 0x51, 0x49, 0x5f, 0xba, 0x58, 0x1c,\n+ 0x4a, 0x16, 0xd5, 0x17, 0xa8, 0x92, 0x24, 0x1f,\n+ 0x8c, 0xff, 0xd8, 0xae, 0x2e, 0x01, 0xd3, 0xad,\n+ 0x3b, 0x4b, 0xda, 0x46, 0xeb, 0xc9, 0xde, 0x9a,\n+ 0x8f, 0x87, 0xd7, 0x3a, 0x80, 0x6f, 0x2f, 0xc8,\n+ 0xb1, 0xb4, 0x37, 0xf7, 0x0a, 0x22, 0x13, 0x28,\n+ 0x7c, 0xcc, 0x3c, 0x89, 0xc7, 0xc3, 0x96, 0x56,\n+ 0x07, 0xbf, 0x7e, 0xf0, 0x0b, 0x2b, 0x97, 0x52,\n+ 0x35, 0x41, 0x79, 0x61, 0xa6, 0x4c, 0x10, 0xfe,\n+ 0xbc, 0x26, 0x95, 0x88, 0x8a, 0xb0, 0xa3, 0xfb,\n+ 0xc0, 0x18, 0x94, 0xf2, 0xe1, 0xe5, 0xe9, 0x5d,\n+ 0xd0, 0xdc, 0x11, 0x66, 0x64, 0x5c, 0xec, 0x59,\n+ 0x42, 0x75, 0x12, 0xf5, 0x74, 0x9c, 0xaa, 0x23,\n+ 0x0e, 0x86, 0xab, 0xbe, 0x2a, 0x02, 0xe7, 0x67,\n+ 0xe6, 0x44, 0xa2, 0x6c, 0xc2, 0x93, 0x9f, 0xf1,\n+ 0xf6, 0xfa, 0x36, 0xd2, 0x50, 0x68, 0x9e, 0x62,\n+ 0x71, 0x15, 0x3d, 0xd6, 0x40, 0xc4, 0xe2, 0x0f,\n+ 0x8e, 0x83, 0x77, 0x6b, 0x25, 0x05, 0x3f, 0x0c,\n+ 0x30, 0xea, 0x70, 0xb7, 0xa1, 0xe8, 0xa9, 0x65,\n+ 0x8d, 0x27, 0x1a, 0xdb, 0x81, 0xb3, 0xa0, 0xf4,\n+ 0x45, 0x7a, 0x19, 0xdf, 0xee, 0x78, 0x34, 0x60,\n+};\n+\n+static const uint8_t octeon_zuc_s1[256] = {\n+ 0x55, 0xc2, 0x63, 0x71, 0x3b, 0xc8, 0x47, 0x86,\n+ 0x9f, 0x3c, 0xda, 0x5b, 0x29, 0xaa, 0xfd, 0x77,\n+ 0x8c, 0xc5, 0x94, 0x0c, 0xa6, 0x1a, 0x13, 0x00,\n+ 0xe3, 0xa8, 0x16, 0x72, 0x40, 0xf9, 0xf8, 0x42,\n+ 0x44, 0x26, 0x68, 0x96, 0x81, 0xd9, 0x45, 0x3e,\n+ 0x10, 0x76, 0xc6, 0xa7, 0x8b, 0x39, 0x43, 0xe1,\n+ 0x3a, 0xb5, 0x56, 0x2a, 0xc0, 0x6d, 0xb3, 0x05,\n+ 0x22, 0x66, 0xbf, 0xdc, 0x0b, 0xfa, 0x62, 0x48,\n+ 0xdd, 0x20, 0x11, 0x06, 0x36, 0xc9, 0xc1, 0xcf,\n+ 0xf6, 0x27, 0x52, 0xbb, 0x69, 0xf5, 0xd4, 0x87,\n+ 0x7f, 0x84, 0x4c, 0xd2, 0x9c, 0x57, 0xa4, 0xbc,\n+ 0x4f, 0x9a, 0xdf, 0xfe, 0xd6, 0x8d, 0x7a, 0xeb,\n+ 0x2b, 0x53, 0xd8, 0x5c, 0xa1, 0x14, 0x17, 0xfb,\n+ 0x23, 0xd5, 0x7d, 0x30, 0x67, 0x73, 0x08, 0x09,\n+ 0xee, 0xb7, 0x70, 0x3f, 0x61, 0xb2, 0x19, 0x8e,\n+ 0x4e, 0xe5, 0x4b, 0x93, 0x8f, 0x5d, 0xdb, 0xa9,\n+ 0xad, 0xf1, 0xae, 0x2e, 0xcb, 0x0d, 0xfc, 0xf4,\n+ 0x2d, 0x46, 0x6e, 0x1d, 0x97, 0xe8, 0xd1, 0xe9,\n+ 0x4d, 0x37, 0xa5, 0x75, 0x5e, 0x83, 0x9e, 0xab,\n+ 0x82, 0x9d, 0xb9, 0x1c, 0xe0, 0xcd, 0x49, 0x89,\n+ 0x01, 0xb6, 0xbd, 0x58, 0x24, 0xa2, 0x5f, 0x38,\n+ 0x78, 0x99, 0x15, 0x90, 0x50, 0xb8, 0x95, 0xe4,\n+ 0xd0, 0x91, 0xc7, 0xce, 0xed, 0x0f, 0xb4, 0x6f,\n+ 0xa0, 0xcc, 0xf0, 0x02, 0x4a, 0x79, 0xc3, 0xde,\n+ 0xa3, 0xef, 0xea, 0x51, 0xe6, 0x6b, 0x18, 0xec,\n+ 0x1b, 0x2c, 0x80, 0xf7, 0x74, 0xe7, 0xff, 0x21,\n+ 0x5a, 0x6a, 0x54, 0x1e, 0x41, 0x31, 0x92, 0x35,\n+ 0xc4, 0x33, 0x07, 0x0a, 0xba, 0x7e, 0x0e, 0x34,\n+ 0x88, 0xb1, 0x98, 0x7c, 0xf3, 0x3d, 0x60, 0x6c,\n+ 0x7b, 0xca, 0xd3, 0x1f, 0x32, 0x65, 0x04, 0x28,\n+ 0x64, 0xbe, 0x85, 0x9b, 0x2f, 0x59, 0x8a, 0xd7,\n+ 0xb0, 0x25, 0xac, 0xaf, 0x12, 0x03, 0xe2, 0xf2,\n+};\n+\n+static inline uint32_t octeon_zuc_addm(uint32_t a, uint32_t b)\n+{\n+ uint32_t c = a + b;\n+\n+ c = (c & 0x7fffffffU) + (c >> 31);\n+ return c ? c : 0x7fffffffU;\n+}\n+\n+static inline uint32_t octeon_zuc_mul_by_pow2(uint32_t v, unsigned int shift)\n+{\n+ return ((v << shift) | (v >> (31 - shift))) & 0x7fffffffU;\n+}\n+\n+static inline uint32_t octeon_zuc_make_u32(uint8_t a, uint8_t b,\n+ uint8_t c, uint8_t d)\n+{\n+ return ((uint32_t)a << 24) | ((uint32_t)b << 16) |\n+ ((uint32_t)c << 8) | d;\n+}\n+\n+static inline uint64_t octeon_zuc_pack_pair(uint32_t hi, uint32_t lo)\n+{\n+ return ((uint64_t)hi << 32) | lo;\n+}\n+\n+static void octeon_zuc_bit_reorganization(const MIPSOcteonCryptoState *crypto,\n+ uint32_t x[4])\n+{\n+ x[0] = ((crypto->zuc_lfsr[15] & 0x7fff8000U) << 1) |\n+ (crypto->zuc_lfsr[14] & 0xffffU);\n+ x[1] = ((crypto->zuc_lfsr[11] & 0xffffU) << 16) |\n+ (crypto->zuc_lfsr[9] >> 15);\n+ x[2] = ((crypto->zuc_lfsr[7] & 0xffffU) << 16) |\n+ (crypto->zuc_lfsr[5] >> 15);\n+ x[3] = ((crypto->zuc_lfsr[2] & 0xffffU) << 16) |\n+ (crypto->zuc_lfsr[0] >> 15);\n+}\n+\n+static inline uint32_t octeon_zuc_l1(uint32_t x)\n+{\n+ return x ^ rol32(x, 2) ^ rol32(x, 10) ^\n+ rol32(x, 18) ^ rol32(x, 24);\n+}\n+\n+static inline uint32_t octeon_zuc_l2(uint32_t x)\n+{\n+ return x ^ rol32(x, 8) ^ rol32(x, 14) ^\n+ rol32(x, 22) ^ rol32(x, 30);\n+}\n+\n+static uint32_t octeon_zuc_f(MIPSOcteonCryptoState *crypto, const uint32_t x[4])\n+{\n+ uint32_t w = (x[0] ^ crypto->zuc_fsm[0]) + crypto->zuc_fsm[1];\n+ uint32_t w1 = crypto->zuc_fsm[0] + x[1];\n+ uint32_t w2 = crypto->zuc_fsm[1] ^ x[2];\n+ uint32_t u = octeon_zuc_l1((w1 << 16) | (w2 >> 16));\n+ uint32_t v = octeon_zuc_l2((w2 << 16) | (w1 >> 16));\n+\n+ crypto->zuc_fsm[0] = octeon_zuc_make_u32(octeon_zuc_s0[u >> 24],\n+ octeon_zuc_s1[(uint8_t)(u >> 16)],\n+ octeon_zuc_s0[(uint8_t)(u >> 8)],\n+ octeon_zuc_s1[(uint8_t)u]);\n+ crypto->zuc_fsm[1] = octeon_zuc_make_u32(octeon_zuc_s0[v >> 24],\n+ octeon_zuc_s1[(uint8_t)(v >> 16)],\n+ octeon_zuc_s0[(uint8_t)(v >> 8)],\n+ octeon_zuc_s1[(uint8_t)v]);\n+ return w;\n+}\n+\n+static void octeon_zuc_lfsr_step(MIPSOcteonCryptoState *crypto,\n+ bool init_mode, uint32_t u)\n+{\n+ uint32_t f = crypto->zuc_lfsr[0];\n+\n+ f = octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(crypto->zuc_lfsr[0], 8));\n+ f = octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(crypto->zuc_lfsr[4], 20));\n+ f = octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(crypto->zuc_lfsr[10], 21));\n+ f = octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(crypto->zuc_lfsr[13], 17));\n+ f = octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(crypto->zuc_lfsr[15], 15));\n+ if (init_mode) {\n+ f = octeon_zuc_addm(f, u);\n+ }\n+\n+ memmove(&crypto->zuc_lfsr[0], &crypto->zuc_lfsr[1],\n+ 15 * sizeof(crypto->zuc_lfsr[0]));\n+ crypto->zuc_lfsr[15] = f;\n+}\n+\n+static uint32_t octeon_zuc_generate_word(MIPSOcteonCryptoState *crypto)\n+{\n+ uint32_t x[4];\n+ uint32_t z;\n+\n+ octeon_zuc_bit_reorganization(crypto, x);\n+ z = octeon_zuc_f(crypto, x) ^ x[3];\n+ octeon_zuc_lfsr_step(crypto, false, 0);\n+ return z;\n+}\n+\n+static void octeon_zuc_fill_window(MIPSOcteonCryptoState *crypto)\n+{\n+ crypto->zuc_window[0] = octeon_zuc_generate_word(crypto);\n+ crypto->zuc_window[1] = octeon_zuc_generate_word(crypto);\n+ crypto->zuc_window[2] = octeon_zuc_generate_word(crypto);\n+}\n+\n+static inline uint32_t\n+octeon_zuc_window_word(const MIPSOcteonCryptoState *crypto, unsigned int bit)\n+{\n+ if (bit == 0) {\n+ return crypto->zuc_window[0];\n+ }\n+ if (bit < 32) {\n+ return (crypto->zuc_window[0] << bit) |\n+ (crypto->zuc_window[1] >> (32 - bit));\n+ }\n+ if (bit == 32) {\n+ return crypto->zuc_window[1];\n+ }\n+ return (crypto->zuc_window[1] << (bit - 32)) |\n+ (crypto->zuc_window[2] >> (64 - bit));\n+}\n+\n+static void octeon_zuc_advance_window(MIPSOcteonCryptoState *crypto)\n+{\n+ crypto->zuc_window[0] = crypto->zuc_window[2];\n+ crypto->zuc_window[1] = octeon_zuc_generate_word(crypto);\n+ crypto->zuc_window[2] = octeon_zuc_generate_word(crypto);\n+}\n+\n+static void octeon_zuc_start(MIPSOcteonCryptoState *crypto, uint64_t q)\n+{\n+ uint32_t x[4];\n+ bool restore_active = crypto->shared_mode == OCTEON_SHARED_MODE_ZUC;\n+\n+ octeon_set_shared_mode(crypto, OCTEON_SHARED_MODE_ZUC);\n+ if (!restore_active) {\n+ for (int i = 0; i < 7; i++) {\n+ uint64_t pair = crypto->sha512_block[i];\n+\n+ crypto->zuc_lfsr[i * 2] = (pair >> 32) & 0x7fffffffU;\n+ crypto->zuc_lfsr[i * 2 + 1] = pair & 0x7fffffffU;\n+ }\n+ }\n+ crypto->zuc_lfsr[14] = (q >> 32) & 0x7fffffffU;\n+ crypto->zuc_lfsr[15] = q & 0x7fffffffU;\n+ crypto->zuc_fsm[0] = 0;\n+ crypto->zuc_fsm[1] = 0;\n+ crypto->zuc_tresult = 0;\n+\n+ for (int i = 0; i < 32; i++) {\n+ octeon_zuc_bit_reorganization(crypto, x);\n+ octeon_zuc_lfsr_step(crypto, true, octeon_zuc_f(crypto, x) >> 1);\n+ }\n+\n+ octeon_zuc_bit_reorganization(crypto, x);\n+ (void)octeon_zuc_f(crypto, x);\n+ octeon_zuc_lfsr_step(crypto, false, 0);\n+ octeon_zuc_fill_window(crypto);\n+}\n+\n+static void octeon_zuc_more(MIPSOcteonCryptoState *crypto, uint64_t q)\n+{\n+ uint32_t t = crypto->zuc_tresult;\n+\n+ octeon_set_shared_mode(crypto, OCTEON_SHARED_MODE_ZUC);\n+ for (unsigned int bit = 0; bit < 64; bit++) {\n+ if ((q >> (63 - bit)) & 1) {\n+ t ^= octeon_zuc_window_word(crypto, bit);\n+ }\n+ }\n+ crypto->zuc_tresult = t;\n+ octeon_zuc_advance_window(crypto);\n+}\n+\n static const uint8_t octeon_snow3g_sr[256] = {\n 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,\n 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,\n@@ -1487,6 +1732,38 @@ target_ulong helper_octeon_cop2_dmfc2(CPUMIPSState *env, uint32_t sel)\n MIPSOcteonCryptoState *crypto = &env->octeon_crypto;\n int sha3_pos;\n \n+ if (crypto->shared_mode == OCTEON_SHARED_MODE_ZUC) {\n+ if (sel >= OCTEON_COP2_SEL_HSH_DATW0 &&\n+ sel <= OCTEON_COP2_SEL_HSH_DATW7) {\n+ unsigned int idx = sel - OCTEON_COP2_SEL_HSH_DATW0;\n+\n+ return octeon_zuc_pack_pair(crypto->zuc_lfsr[idx * 2],\n+ crypto->zuc_lfsr[idx * 2 + 1]);\n+ }\n+ switch (sel) {\n+ case OCTEON_COP2_SEL_HSH_DATW8:\n+ return octeon_zuc_pack_pair(crypto->zuc_fsm[0], crypto->zuc_fsm[1]);\n+ case OCTEON_COP2_SEL_HSH_DATW9:\n+ case OCTEON_COP2_SEL_HSH_IVW0:\n+ return octeon_zuc_pack_pair(crypto->zuc_window[0],\n+ crypto->zuc_window[1]);\n+ case OCTEON_COP2_SEL_HSH_DATW10:\n+ return crypto->zuc_window[2];\n+ case OCTEON_COP2_SEL_HSH_DATW11:\n+ case OCTEON_COP2_SEL_HSH_IVW3:\n+ return crypto->zuc_tresult;\n+ case OCTEON_COP2_SEL_SHA3_DAT15_READ:\n+ case OCTEON_COP2_SEL_SHA3_DAT24:\n+ return 0;\n+ case OCTEON_COP2_SEL_HSH_IVW1:\n+ return crypto->zuc_fsm[0];\n+ case OCTEON_COP2_SEL_HSH_IVW2:\n+ return crypto->zuc_fsm[1];\n+ default:\n+ break;\n+ }\n+ }\n+\n if (crypto->shared_mode == OCTEON_SHARED_MODE_SNOW3G) {\n if (sel >= OCTEON_COP2_SEL_SNOW3G_LFSR0 &&\n sel <= OCTEON_COP2_SEL_SNOW3G_LFSR7) {\n@@ -1606,6 +1883,46 @@ void helper_octeon_cop2_dmtc2(CPUMIPSState *env, target_ulong value,\n uint64_t q = (uint64_t)value;\n int sha3_pos;\n \n+ if (crypto->shared_mode == OCTEON_SHARED_MODE_ZUC) {\n+ if (sel >= OCTEON_COP2_SEL_HSH_DATW0 &&\n+ sel <= OCTEON_COP2_SEL_HSH_DATW7) {\n+ unsigned int idx = sel - OCTEON_COP2_SEL_HSH_DATW0;\n+\n+ crypto->zuc_lfsr[idx * 2] = (q >> 32) & 0x7fffffffU;\n+ crypto->zuc_lfsr[idx * 2 + 1] = q & 0x7fffffffU;\n+ return;\n+ }\n+ switch (sel) {\n+ case OCTEON_COP2_SEL_HSH_DATW8:\n+ crypto->zuc_fsm[0] = q >> 32;\n+ crypto->zuc_fsm[1] = q;\n+ return;\n+ case OCTEON_COP2_SEL_HSH_DATW9:\n+ case OCTEON_COP2_SEL_HSH_IVW0:\n+ crypto->zuc_window[0] = q >> 32;\n+ crypto->zuc_window[1] = q;\n+ return;\n+ case OCTEON_COP2_SEL_HSH_DATW10:\n+ crypto->zuc_window[2] = q;\n+ return;\n+ case OCTEON_COP2_SEL_HSH_DATW11:\n+ case OCTEON_COP2_SEL_HSH_IVW3:\n+ crypto->zuc_tresult = q;\n+ return;\n+ case OCTEON_COP2_SEL_SHA3_DAT15_WRITE:\n+ case OCTEON_COP2_SEL_SHA3_DAT24:\n+ return;\n+ case OCTEON_COP2_SEL_HSH_IVW1:\n+ crypto->zuc_fsm[0] = q;\n+ return;\n+ case OCTEON_COP2_SEL_HSH_IVW2:\n+ crypto->zuc_fsm[1] = q;\n+ return;\n+ default:\n+ break;\n+ }\n+ }\n+\n switch (sel) {\n case OCTEON_COP2_SEL_3DES_KEY0:\n case OCTEON_COP2_SEL_3DES_KEY1:\n@@ -1822,6 +2139,12 @@ void helper_octeon_cop2_dmtc2(CPUMIPSState *env, target_ulong value,\n octeon_set_shared_mode(crypto, OCTEON_SHARED_MODE_SHA3);\n octeon_sha3_permute(crypto);\n break;\n+ case OCTEON_COP2_SEL_ZUC_START:\n+ octeon_zuc_start(crypto, q);\n+ break;\n+ case OCTEON_COP2_SEL_ZUC_MORE:\n+ octeon_zuc_more(crypto, q);\n+ break;\n case OCTEON_COP2_SEL_GFM_XORMUL1_REFLECT:\n octeon_gfm_mul_reflect(crypto, q);\n break;\ndiff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex be380cab11..39fad07adc 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -9303,6 +9303,8 @@ static bool octeon_cop2_is_supported_dmtc2(uint16_t sel)\n case OCTEON_COP2_SEL_SNOW3G_MORE:\n case OCTEON_COP2_SEL_HSH_STARTSHA256:\n case OCTEON_COP2_SEL_SHA3_STARTOP:\n+ case OCTEON_COP2_SEL_ZUC_START:\n+ case OCTEON_COP2_SEL_ZUC_MORE:\n case OCTEON_COP2_SEL_HSH_STARTSHA1:\n case OCTEON_COP2_SEL_GFM_XORMUL1_REFLECT:\n case OCTEON_COP2_SEL_HSH_STARTSHA512:\n", "prefixes": [ "7/9" ] }