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GET /api/1.1/patches/2221595/?format=api
{ "id": 2221595, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221595/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-7-lucaaamaral@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409220614.65558-7-lucaaamaral@gmail.com>", "date": "2026-04-09T22:06:14", "name": "[v6,6/6] target/arm/hvf, whpx: wire ISV=0 emulation for data aborts", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "136c45b214afcc31aeef91cd81cd5dd0494f6762", "submitter": { "id": 92822, "url": "http://patchwork.ozlabs.org/api/1.1/people/92822/?format=api", "name": "Lucas Amaral", "email": "lucaaamaral@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-7-lucaaamaral@gmail.com/mbox/", "series": [ { "id": 499365, "url": "http://patchwork.ozlabs.org/api/1.1/series/499365/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499365", "date": "2026-04-09T22:06:14", "name": null, "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499365/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221595/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221595/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=kMhxRzX+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-dy1-x1332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When a data abort with ISV=0 occurs during MMIO emulation, the\nsyndrome register does not carry the access size or target register.\nPreviously this hit an assert(isv) and killed the VM.\n\nReplace the assert with instruction fetch + decode + emulate using the\nshared library in target/arm/emulate/. The faulting instruction is read\nfrom guest memory via cpu_memory_rw_debug(), decoded by the decodetree-\ngenerated decoder, and emulated against the vCPU register file.\n\nBoth HVF (macOS) and WHPX (Windows Hyper-V) use the same pattern:\n 1. cpu_synchronize_state() to flush hypervisor registers\n 2. Fetch 4-byte instruction at env->pc\n 3. arm_emul_insn(env, insn)\n 4. On success, advance PC past the emulated instruction\n\nIf the instruction is unhandled or a memory error occurs, a synchronous\nexternal abort is injected into the guest via syn_data_abort_no_iss()\nwith fnv=1 and fsc=0x10, matching the syndrome that KVM uses in\nkvm_inject_arm_sea(). The guest kernel's fault handler then reports\nthe error through its normal data abort path.\n\nWHPX adds a whpx_inject_data_abort() helper and adjusts the\nwhpx_handle_mmio() return convention so the caller skips PC advancement\nwhen an exception has been injected.\n\nSigned-off-by: Lucas Amaral <lucaaamaral@gmail.com>\n---\n target/arm/hvf/hvf.c | 46 ++++++++++++++++++++++++++--\n target/arm/whpx/whpx-all.c | 61 +++++++++++++++++++++++++++++++++++++-\n 2 files changed, 103 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 5fc8f6bb..000e54bd 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -32,6 +32,7 @@\n #include \"arm-powerctl.h\"\n #include \"target/arm/cpu.h\"\n #include \"target/arm/internals.h\"\n+#include \"emulate/arm_emulate.h\"\n #include \"target/arm/multiprocessing.h\"\n #include \"target/arm/gtimer.h\"\n #include \"target/arm/trace.h\"\n@@ -2175,10 +2176,49 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n assert(!s1ptw);\n \n /*\n- * TODO: ISV will be 0 for SIMD or SVE accesses.\n- * Inject the exception into the guest.\n+ * ISV=0: syndrome doesn't carry access size/register info.\n+ * Fetch and emulate via target/arm/emulate/.\n */\n- assert(isv);\n+ if (!isv) {\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ uint32_t insn;\n+ ArmEmulResult r;\n+\n+ cpu_synchronize_state(cpu);\n+\n+ if (cpu_memory_rw_debug(cpu, env->pc,\n+ (uint8_t *)&insn, 4, false) != 0) {\n+ bool same_el = arm_current_el(env) == 1;\n+ uint32_t esr = syn_data_abort_no_iss(same_el,\n+ 1, 0, 0, 0, iswrite, 0x10);\n+\n+ error_report(\"HVF: cannot read insn at pc=0x%\" PRIx64,\n+ (uint64_t)env->pc);\n+ env->exception.vaddress = excp->virtual_address;\n+ hvf_raise_exception(cpu, EXCP_DATA_ABORT, esr, 1);\n+ break;\n+ }\n+\n+ r = arm_emul_insn(env, insn);\n+ if (r == ARM_EMUL_UNHANDLED || r == ARM_EMUL_ERR_MEM) {\n+ bool same_el = arm_current_el(env) == 1;\n+ uint32_t esr = syn_data_abort_no_iss(same_el,\n+ 1, 0, 0, 0, iswrite, 0x10);\n+\n+ error_report(\"HVF: ISV=0 %s insn 0x%08x at \"\n+ \"pc=0x%\" PRIx64 \", injecting data abort\",\n+ r == ARM_EMUL_UNHANDLED ? \"unhandled\"\n+ : \"memory error\",\n+ insn, (uint64_t)env->pc);\n+ env->exception.vaddress = excp->virtual_address;\n+ hvf_raise_exception(cpu, EXCP_DATA_ABORT, esr, 1);\n+ break;\n+ }\n+\n+ advance_pc = true;\n+ break;\n+ }\n \n /*\n * Emulate MMIO.\ndiff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\nindex 513551be..0c04073e 100644\n--- a/target/arm/whpx/whpx-all.c\n+++ b/target/arm/whpx/whpx-all.c\n@@ -29,6 +29,7 @@\n #include \"syndrome.h\"\n #include \"target/arm/cpregs.h\"\n #include \"internals.h\"\n+#include \"emulate/arm_emulate.h\"\n \n #include \"system/whpx-internal.h\"\n #include \"system/whpx-accel-ops.h\"\n@@ -352,6 +353,27 @@ static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val)\n whpx_set_reg(cpu, reg, reg_val);\n }\n \n+/*\n+ * Inject a synchronous external abort (data abort) into the guest.\n+ * Used when ISV=0 instruction emulation fails. Matches the syndrome\n+ * that KVM uses in kvm_inject_arm_sea().\n+ */\n+static void whpx_inject_data_abort(CPUState *cpu, bool iswrite)\n+{\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ bool same_el = arm_current_el(env) == 1;\n+ uint32_t esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, iswrite, 0x10);\n+\n+ cpu->exception_index = EXCP_DATA_ABORT;\n+ env->exception.target_el = 1;\n+ env->exception.syndrome = esr;\n+\n+ bql_lock();\n+ arm_cpu_do_interrupt(cpu);\n+ bql_unlock();\n+}\n+\n static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n {\n uint64_t syndrome = ctx->Syndrome;\n@@ -366,7 +388,40 @@ static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n uint64_t val = 0;\n \n assert(!cm);\n- assert(isv);\n+\n+ /*\n+ * ISV=0: syndrome doesn't carry access size/register info.\n+ * Fetch and decode the faulting instruction via the emulation library.\n+ */\n+ if (!isv) {\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+ uint32_t insn;\n+ ArmEmulResult r;\n+\n+ cpu_synchronize_state(cpu);\n+\n+ if (cpu_memory_rw_debug(cpu, env->pc,\n+ (uint8_t *)&insn, 4, false) != 0) {\n+ error_report(\"WHPX: cannot read insn at pc=0x%\" PRIx64,\n+ (uint64_t)env->pc);\n+ whpx_inject_data_abort(cpu, iswrite);\n+ return 1;\n+ }\n+\n+ r = arm_emul_insn(env, insn);\n+ if (r == ARM_EMUL_UNHANDLED || r == ARM_EMUL_ERR_MEM) {\n+ error_report(\"WHPX: ISV=0 %s insn 0x%08x at \"\n+ \"pc=0x%\" PRIx64 \", injecting data abort\",\n+ r == ARM_EMUL_UNHANDLED ? \"unhandled\"\n+ : \"memory error\",\n+ insn, (uint64_t)env->pc);\n+ whpx_inject_data_abort(cpu, iswrite);\n+ return 1;\n+ }\n+\n+ return 0;\n+ }\n \n if (iswrite) {\n val = whpx_get_gp_reg(cpu, srt);\n@@ -451,6 +506,10 @@ int whpx_vcpu_run(CPUState *cpu)\n }\n \n ret = whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess);\n+ if (ret > 0) {\n+ advance_pc = false;\n+ ret = 0;\n+ }\n break;\n case WHvRunVpExitReasonCanceled:\n cpu->exception_index = EXCP_INTERRUPT;\n", "prefixes": [ "v6", "6/6" ] }