[{"id":3675527,"web_url":"http://patchwork.ozlabs.org/comment/3675527/","msgid":"<4303E81D-5539-4666-BBE8-BA58E3F72B6F@unpredictable.fr>","list_archive_url":null,"date":"2026-04-09T22:12:54","subject":"Re: [PATCH v6 6/6] target/arm/hvf,\n whpx: wire ISV=0 emulation for data\n aborts","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 10. Apr 2026, at 00:06, Lucas Amaral wrote:\n> \n> When a data abort with ISV=0 occurs during MMIO emulation, the\n> syndrome register does not carry the access size or target register.\n> Previously this hit an assert(isv) and killed the VM.\n> \n> Replace the assert with instruction fetch + decode + emulate using the\n> shared library in target/arm/emulate/. The faulting instruction is read\n> from guest memory via cpu_memory_rw_debug(), decoded by the decodetree-\n> generated decoder, and emulated against the vCPU register file.\n> \n> Both HVF (macOS) and WHPX (Windows Hyper-V) use the same pattern:\n> 1. cpu_synchronize_state() to flush hypervisor registers\n> 2. Fetch 4-byte instruction at env->pc\n> 3. arm_emul_insn(env, insn)\n> 4. On success, advance PC past the emulated instruction\n> \n> If the instruction is unhandled or a memory error occurs, a synchronous\n> external abort is injected into the guest via syn_data_abort_no_iss()\n> with fnv=1 and fsc=0x10, matching the syndrome that KVM uses in\n> kvm_inject_arm_sea(). The guest kernel's fault handler then reports\n> the error through its normal data abort path.\n> \n> WHPX adds a whpx_inject_data_abort() helper and adjusts the\n> whpx_handle_mmio() return convention so the caller skips PC advancement\n> when an exception has been injected.\n> \n> Signed-off-by: Lucas Amaral \n> ---\n> target/arm/hvf/hvf.c | 46 ++++++++++++++++++++++++++--\n> target/arm/whpx/whpx-all.c | 61 +++++++++++++++++++++++++++++++++++++-\n> 2 files changed, 103 insertions(+), 4 deletions(-)\n> \n> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\n> index 5fc8f6bb..000e54bd 100644\n> --- a/target/arm/hvf/hvf.c\n> +++ b/target/arm/hvf/hvf.c\n> @@ -32,6 +32,7 @@\n> #include \"arm-powerctl.h\"\n> #include \"target/arm/cpu.h\"\n> #include \"target/arm/internals.h\"\n> +#include \"emulate/arm_emulate.h\"\n> #include \"target/arm/multiprocessing.h\"\n> #include \"target/arm/gtimer.h\"\n> #include \"target/arm/trace.h\"\n> @@ -2175,10 +2176,49 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n> assert(!s1ptw);\n> \n> /*\n> - * TODO: ISV will be 0 for SIMD or SVE accesses.\n> - * Inject the exception into the guest.\n> + * ISV=0: syndrome doesn't carry access size/register info.\n> + * Fetch and emulate via target/arm/emulate/.\n> */\n> - assert(isv);\n> + if (!isv) {\n> + ARMCPU *arm_cpu = ARM_CPU(cpu);\n> + CPUARMState *env = &arm_cpu->env;\n> + uint32_t insn;\n> + ArmEmulResult r;\n> +\n> + cpu_synchronize_state(cpu);\n> +\n> + if (cpu_memory_rw_debug(cpu, env->pc,\n> + (uint8_t *)&insn, 4, false) != 0) {\nHello,\n\nHaving a version of mem_access exported and used there too to read the instruction\nto get rid of cpu_memory_rw_debug there too\n\n(For both WHPX and HVF)\n\n> + bool same_el = arm_current_el(env) == 1;\n> + uint32_t esr = syn_data_abort_no_iss(same_el,\n> + 1, 0, 0, 0, iswrite, 0x10);\n> +\n> + error_report(\"HVF: cannot read insn at pc=0x%\" PRIx64,\n> + (uint64_t)env->pc);\n> + env->exception.vaddress = excp->virtual_address;\n> + hvf_raise_exception(cpu, EXCP_DATA_ABORT, esr, 1);\n> + break;\n> + }\n> +\n> + r = arm_emul_insn(env, insn);\n> + if (r == ARM_EMUL_UNHANDLED || r == ARM_EMUL_ERR_MEM) {\n> + bool same_el = arm_current_el(env) == 1;\n> + uint32_t esr = syn_data_abort_no_iss(same_el,\n> + 1, 0, 0, 0, iswrite, 0x10);\n> +\n> + error_report(\"HVF: ISV=0 %s insn 0x%08x at \"\n> + \"pc=0x%\" PRIx64 \", injecting data abort\",\n> + r == ARM_EMUL_UNHANDLED ? \"unhandled\"\n> + : \"memory error\",\n> + insn, (uint64_t)env->pc);\n> + env->exception.vaddress = excp->virtual_address;\n> + hvf_raise_exception(cpu, EXCP_DATA_ABORT, esr, 1);\n> + break;\n> + }\n> +\n> + advance_pc = true;\n> + break;\n> + }\n> \n> /*\n> * Emulate MMIO.\n> diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\n> index 513551be..0c04073e 100644\n> --- a/target/arm/whpx/whpx-all.c\n> +++ b/target/arm/whpx/whpx-all.c\n> @@ -29,6 +29,7 @@\n> #include \"syndrome.h\"\n> #include \"target/arm/cpregs.h\"\n> #include \"internals.h\"\n> +#include \"emulate/arm_emulate.h\"\n> \n> #include \"system/whpx-internal.h\"\n> #include \"system/whpx-accel-ops.h\"\n> @@ -352,6 +353,27 @@ static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val)\n> whpx_set_reg(cpu, reg, reg_val);\n> }\n> \n> +/*\n> + * Inject a synchronous external abort (data abort) into the guest.\n> + * Used when ISV=0 instruction emulation fails. Matches the syndrome\n> + * that KVM uses in kvm_inject_arm_sea().\n> + */\n> +static void whpx_inject_data_abort(CPUState *cpu, bool iswrite)\n> +{\n> + ARMCPU *arm_cpu = ARM_CPU(cpu);\n> + CPUARMState *env = &arm_cpu->env;\n> + bool same_el = arm_current_el(env) == 1;\n> + uint32_t esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, iswrite, 0x10);\n> +\n> + cpu->exception_index = EXCP_DATA_ABORT;\n> + env->exception.target_el = 1;\n> + env->exception.syndrome = esr;\n> +\n> + bql_lock();\n> + arm_cpu_do_interrupt(cpu);\n> + bql_unlock();\n> +}\n> +\n> static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n> {\n> uint64_t syndrome = ctx->Syndrome;\n> @@ -366,7 +388,40 @@ static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n> uint64_t val = 0;\n> \n> assert(!cm);\n> - assert(isv);\n> +\n> + /*\n> + * ISV=0: syndrome doesn't carry access size/register info.\n> + * Fetch and decode the faulting instruction via the emulation library.\n> + */\n> + if (!isv) {\n> + ARMCPU *arm_cpu = ARM_CPU(cpu);\n> + CPUARMState *env = &arm_cpu->env;\n> + uint32_t insn;\n> + ArmEmulResult r;\n> +\n> + cpu_synchronize_state(cpu);\n> +\n> + if (cpu_memory_rw_debug(cpu, env->pc,\n> + (uint8_t *)&insn, 4, false) != 0) {\n> + error_report(\"WHPX: cannot read insn at pc=0x%\" PRIx64,\n> + (uint64_t)env->pc);\n> + whpx_inject_data_abort(cpu, iswrite);\n> + return 1;\n> + }\n> +\n> + r = arm_emul_insn(env, insn);\n> + if (r == ARM_EMUL_UNHANDLED || r == ARM_EMUL_ERR_MEM) {\n> + error_report(\"WHPX: ISV=0 %s insn 0x%08x at \"\n> + \"pc=0x%\" PRIx64 \", injecting data abort\",\n> + r == ARM_EMUL_UNHANDLED ? \"unhandled\"\n> + : \"memory error\",\n> + insn, (uint64_t)env->pc);\n> + whpx_inject_data_abort(cpu, iswrite);\n> + return 1;\n> + }\n> +\n> + return 0;\n> + }\n> \n> if (iswrite) {\n> val = whpx_get_gp_reg(cpu, srt);\n> @@ -451,6 +506,10 @@ int whpx_vcpu_run(CPUState *cpu)\n> }\n> \n> ret = whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess);\n> + if (ret > 0) {\n> + advance_pc = false;\n> + ret = 0;\n> + }\n> break;\n> case WHvRunVpExitReasonCanceled:\n> cpu->exception_index = EXCP_INTERRUPT;\n> -- \n> 2.52.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=NrsDYl2r;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.st.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-to":"Mohamed Mediouni ","From":"Mohamed Mediouni via qemu development ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3675660,"web_url":"http://patchwork.ozlabs.org/comment/3675660/","msgid":"<20260410052004.79395-1-lucaaamaral@gmail.com>","list_archive_url":null,"date":"2026-04-10T05:20:04","subject":"Re: [PATCH v6 0/6] target/arm: ISV=0 data abort emulation library","submitter":{"id":92822,"url":"http://patchwork.ozlabs.org/api/people/92822/","name":"Lucas Amaral","email":"lucaaamaral@gmail.com"},"content":"Hi Mohamed,\n\nThanks for the thorough review and the Reviewed-by tags on all six\npatches.\n\nOn the observations:\n\n> [1/6] Perhaps having a common version of this for fetching the\n> instruction\n\nGood point. The ISV=0 wiring in target/arm/hvf/hvf.c and\ntarget/arm/whpx/whpx-all.c still uses cpu_memory_rw_debug() to fetch\nthe faulting instruction at env->pc — Henderson flagged this for the\nlibrary code in v5, but the wiring code was out of scope for v6. I'll\ninvestigate factoring out a common get_phys_addr() + address_space_rw\nhelper covering both call sites and send it as a follow-up.\n\n> [4/6] Do people actually use [exclusive load/store on MMIO]? And if\n> so I wonder if that's an application bug...\n\nI had the impression that virglrenderer hit this early on, but I'm\nnot 100% sure of the exact case anymore. The v4 emulation library\ntried to cover the most likely ISV=0 triggers — load/store pair,\nregister-offset, exclusives, atomics, CAS — without fully exhausting\nthe ISA. I might double-check what actually exercises this path in\npractice.\n\n> [5/6] Maybe there should be a restriction to put a warning message\n> somewhere if an op happens on a non-MMIO range...\n\nAgreed, that would help debug guest issues. I'll look into adding a\nwarn_report_once() when get_phys_addr() resolves to a RAM region (vs\nMMIO/Device).\n\nI'll send these as a follow-up series once v6 lands.\n\nThanks,\nLucas","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=E0pG1cCh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsQBH1XDGz1yGb\n\tfor ; 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