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GET /api/1.1/patches/2221594/?format=api
{ "id": 2221594, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221594/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-3-lucaaamaral@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409220614.65558-3-lucaaamaral@gmail.com>", "date": "2026-04-09T22:06:10", "name": "[v6,2/6] target/arm/emulate: add load/store register offset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bab318df6cfff49ec0859617a5685fa18f5ac8ec", "submitter": { "id": 92822, "url": "http://patchwork.ozlabs.org/api/1.1/people/92822/?format=api", "name": "Lucas Amaral", "email": "lucaaamaral@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-3-lucaaamaral@gmail.com/mbox/", "series": [ { "id": 499364, "url": "http://patchwork.ozlabs.org/api/1.1/series/499364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364", "date": "2026-04-09T22:06:10", "name": "target/arm: ISV=0 data abort emulation library", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499364/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221594/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221594/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=YmC3QJvj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1332;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add emulation for load/store register offset addressing mode\n(DDI 0487 C3.3.9). The offset register value is extended via\nUXTB/UXTH/UXTW/UXTX/SXTB/SXTH/SXTW/SXTX and optionally\nshifted by the element size.\n\nInstruction coverage:\n - STR/LDR (GPR): register offset with extend, all sizes\n - STR/LDR (SIMD/FP): register offset with extend, 8-128 bit\n - PRFM register offset: NOP\n\nSigned-off-by: Lucas Amaral <lucaaamaral@gmail.com>\n---\n target/arm/emulate/a64-ldst.decode | 29 ++++++++\n target/arm/emulate/arm_emulate.c | 106 +++++++++++++++++++++++++++++\n 2 files changed, 135 insertions(+)", "diff": "diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\nindex c887dcba..af6babe1 100644\n--- a/target/arm/emulate/a64-ldst.decode\n+++ b/target/arm/emulate/a64-ldst.decode\n@@ -10,6 +10,9 @@\n # 'u' flag: 0 = 9-bit signed immediate (byte offset), 1 = 12-bit unsigned (needs << sz)\n &ldst_imm rt rn imm sz sign w p unpriv ext u\n \n+# Load/store register offset\n+&ldst rm rn rt sign ext sz opt s\n+\n ### Format templates\n \n # Load/store immediate (9-bit signed)\n@@ -21,6 +24,9 @@\n # Load/store unsigned offset (12-bit, handler scales by << sz)\n @ldst_uimm .. ... . .. .. imm:12 rn:5 rt:5 &ldst_imm u=1 unpriv=0 p=0 w=0\n \n+# Load/store register offset\n+@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst\n+\n ### Load/store register — unscaled immediate (LDUR/STUR)\n \n # GPR\n@@ -122,6 +128,29 @@ STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=\n LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0\n LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4\n \n+### Load/store register — register offset\n+\n+# GPR\n+STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0\n+LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0\n+LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1\n+LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2\n+LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3\n+LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0\n+LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1\n+LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2\n+LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0\n+LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1\n+\n+# PRFM — register offset\n+NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----\n+\n+# SIMD/FP\n+STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0\n+STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4\n+LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0\n+LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4\n+\n ### System instructions — DC cache maintenance\n \n # SYS with CRn=C7 covers all data cache operations (DC CIVAC, CVAC, etc.).\ndiff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\nindex bedbdb3e..79f42d44 100644\n--- a/target/arm/emulate/arm_emulate.c\n+++ b/target/arm/emulate/arm_emulate.c\n@@ -263,6 +263,112 @@ static bool trans_LDR_v_i(DisasContext *ctx, arg_ldst_imm *a)\n return true;\n }\n \n+/* Register offset extension (DDI 0487 C6.2.131) */\n+\n+static uint64_t extend_reg(uint64_t val, int option, int shift)\n+{\n+ switch (option) {\n+ case 0: /* UXTB */\n+ val = (uint8_t)val;\n+ break;\n+ case 1: /* UXTH */\n+ val = (uint16_t)val;\n+ break;\n+ case 2: /* UXTW */\n+ val = (uint32_t)val;\n+ break;\n+ case 3: /* UXTX / LSL */\n+ break;\n+ case 4: /* SXTB */\n+ val = (int64_t)(int8_t)val;\n+ break;\n+ case 5: /* SXTH */\n+ val = (int64_t)(int16_t)val;\n+ break;\n+ case 6: /* SXTW */\n+ val = (int64_t)(int32_t)val;\n+ break;\n+ case 7: /* SXTX */\n+ break;\n+ }\n+ return val << shift;\n+}\n+\n+/*\n+ * Load/store single -- register offset (GPR)\n+ * STR / LDR (DDI 0487 C3.3.9)\n+ */\n+\n+static bool trans_STR(DisasContext *ctx, arg_ldst *a)\n+{\n+ int esize = (a->sz <= 3) ? (1 << a->sz) : 16;\n+ int shift = a->s ? a->sz : 0;\n+ uint64_t rm_val = gpr_read(ctx, a->rm);\n+ uint64_t offset = extend_reg(rm_val, a->opt, shift);\n+ uint64_t va = base_read(ctx, a->rn) + offset;\n+\n+ uint8_t buf[16];\n+ uint64_t val = gpr_read(ctx, a->rt);\n+ mem_st(ctx, buf, esize, val);\n+ mem_write(ctx, va, buf, esize);\n+ return true;\n+}\n+\n+static bool trans_LDR(DisasContext *ctx, arg_ldst *a)\n+{\n+ int esize = (a->sz <= 3) ? (1 << a->sz) : 16;\n+ int shift = a->s ? a->sz : 0;\n+ uint64_t rm_val = gpr_read(ctx, a->rm);\n+ uint64_t offset = extend_reg(rm_val, a->opt, shift);\n+ uint64_t va = base_read(ctx, a->rn) + offset;\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ uint64_t val = mem_ld(ctx, buf, esize);\n+ val = load_extend(val, a->sz, a->sign, a->ext);\n+ gpr_write(ctx, a->rt, val);\n+ return true;\n+}\n+\n+/*\n+ * Load/store single -- register offset (SIMD/FP)\n+ * STR_v / LDR_v (DDI 0487 C3.3.10)\n+ */\n+\n+static bool trans_STR_v(DisasContext *ctx, arg_ldst *a)\n+{\n+ int esize = (a->sz <= 3) ? (1 << a->sz) : 16;\n+ int shift = a->s ? a->sz : 0;\n+ uint64_t rm_val = gpr_read(ctx, a->rm);\n+ uint64_t offset = extend_reg(rm_val, a->opt, shift);\n+ uint64_t va = base_read(ctx, a->rn) + offset;\n+ uint8_t buf[16];\n+\n+ fpreg_read(ctx, a->rt, buf, esize);\n+ mem_write(ctx, va, buf, esize);\n+ return true;\n+}\n+\n+static bool trans_LDR_v(DisasContext *ctx, arg_ldst *a)\n+{\n+ int esize = (a->sz <= 3) ? (1 << a->sz) : 16;\n+ int shift = a->s ? a->sz : 0;\n+ uint64_t rm_val = gpr_read(ctx, a->rm);\n+ uint64_t offset = extend_reg(rm_val, a->opt, shift);\n+ uint64_t va = base_read(ctx, a->rn) + offset;\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, esize) != 0) {\n+ return true;\n+ }\n+\n+ fpreg_write(ctx, a->rt, buf, esize);\n+ return true;\n+}\n+\n /* PRFM, DC cache maintenance -- treated as NOP */\n static bool trans_NOP(DisasContext *ctx, arg_NOP *a)\n {\n", "prefixes": [ "v6", "2/6" ] }