[{"id":3675530,"web_url":"http://patchwork.ozlabs.org/comment/3675530/","msgid":"","list_archive_url":null,"date":"2026-04-09T22:14:49","subject":"Re: [PATCH v6 2/6] target/arm/emulate: add load/store register offset","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 10. Apr 2026, at 00:06, Lucas Amaral wrote:\n> \n> Add emulation for load/store register offset addressing mode\n> (DDI 0487 C3.3.9). The offset register value is extended via\n> UXTB/UXTH/UXTW/UXTX/SXTB/SXTH/SXTW/SXTX and optionally\n> shifted by the element size.\n> \n> Instruction coverage:\n> - STR/LDR (GPR): register offset with extend, all sizes\n> - STR/LDR (SIMD/FP): register offset with extend, 8-128 bit\n> - PRFM register offset: NOP\n> \n> Signed-off-by: Lucas Amaral \nReviewed-by: Mohamed Mediouni ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=NMtVJBmz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsDlJ0qKgz1y05\n\tfor ; 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