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GET /api/1.1/patches/2221124/?format=api
{ "id": 2221124, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221124/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-4-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408042149.1902796-4-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:21:42", "name": "[v4,3/9] hw/hexagon: Add machine configs for sysemu", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5f7ea735b7346b8731d7fcb530e6cf781f839c62", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.1/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-4-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499184, "url": "http://patchwork.ozlabs.org/api/1.1/series/499184/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499184", "date": "2026-04-08T04:21:47", "name": "Hexagon system emulation - Part 3/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499184/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221124/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221124/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n 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<sidneym@quicinc.com>, Paolo Bonzini <pbonzini@redhat.com>,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>", "Subject": "[PATCH v4 3/9] hw/hexagon: Add machine configs for sysemu", "Date": "Tue, 7 Apr 2026 21:21:42 -0700", "Message-Id": "<20260408042149.1902796-4-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408042149.1902796-1-brian.cain@oss.qualcomm.com>", "References": "<20260408042149.1902796-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-ORIG-GUID": "QdINQOxwAjg_zd8yfo5R1gbpDuD0O2NL", "X-Proofpoint-GUID": "QdINQOxwAjg_zd8yfo5R1gbpDuD0O2NL", "X-Authority-Analysis": "v=2.4 cv=TOt1jVla c=1 sm=1 tr=0 ts=69d5d7e4 cx=c_pps\n a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 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"rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0 spamscore=0 adultscore=0 impostorscore=0\n lowpriorityscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080036", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nSome header includes are modified here: these are uniquely required for\nbasic system emulation functionality and had not been required for linux-user.\n\nAcked-by: Markus Armbruster <armbru@redhat.com>\nCo-authored-by: Mike Lambert <mlambert@quicinc.com>\nCo-authored-by: Sid Manning <sidneym@quicinc.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n MAINTAINERS | 2 +\n include/hw/hexagon/hexagon.h | 150 +++++++++++++++++++++++\n hw/hexagon/machine_cfg_v66g_1024.h.inc | 64 ++++++++++\n hw/hexagon/hexagon_dsp.c | 161 +++++++++++++++++++++++++\n system/qdev-monitor.c | 2 +-\n target/hexagon/translate.c | 1 +\n hw/Kconfig | 1 +\n hw/hexagon/Kconfig | 5 +\n hw/hexagon/meson.build | 6 +\n hw/meson.build | 1 +\n 10 files changed, 392 insertions(+), 1 deletion(-)\n create mode 100644 include/hw/hexagon/hexagon.h\n create mode 100644 hw/hexagon/machine_cfg_v66g_1024.h.inc\n create mode 100644 hw/hexagon/hexagon_dsp.c\n create mode 100644 hw/hexagon/Kconfig\n create mode 100644 hw/hexagon/meson.build", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 4055fbe3c21..b9a7c553dfa 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -246,6 +246,8 @@ Hexagon TCG CPUs\n M: Brian Cain <brian.cain@oss.qualcomm.com>\n S: Supported\n F: target/hexagon/\n+F: hw/hexagon/\n+F: include/hw/hexagon/\n X: target/hexagon/idef-parser/\n X: target/hexagon/gen_idef_parser_funcs.py\n F: linux-user/hexagon/\ndiff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h\nnew file mode 100644\nindex 00000000000..996f5423c39\n--- /dev/null\n+++ b/include/hw/hexagon/hexagon.h\n@@ -0,0 +1,150 @@\n+/*\n+ * Hexagon Baseboard System emulation.\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+\n+#ifndef HW_HEXAGON_H\n+#define HW_HEXAGON_H\n+\n+#include \"system/memory.h\"\n+\n+struct hexagon_board_boot_info {\n+ uint64_t ram_size;\n+ const char *kernel_filename;\n+ uint32_t kernel_elf_flags;\n+};\n+\n+typedef enum {\n+ unknown_rev = 0,\n+ v66_rev = 0xa666,\n+ v67_rev = 0x2667,\n+ v68_rev = 0x8d68,\n+ v69_rev = 0x8c69,\n+ v71_rev = 0x8c71,\n+ v73_rev = 0x8c73,\n+ v73m_rev = 0xcc73,\n+} Rev_t;\n+#define HEXAGON_LATEST_REV v73\n+#define HEXAGON_LATEST_REV_UPPER V73\n+\n+/*\n+ * Config table address bases represent bits [35:16].\n+ */\n+#define HEXAGON_CFG_ADDR_BASE(addr) (((addr) >> 16) & 0x0fffff)\n+\n+#define HEXAGON_CFGSPACE_ENTRIES (128)\n+\n+union hexagon_config_table {\n+ struct {\n+ /* Base address of L2TCM space */\n+ uint32_t l2tcm_base;\n+ uint32_t reserved0;\n+ /* Base address of subsystem space */\n+ uint32_t subsystem_base;\n+ /* Base address of ETM space */\n+ uint32_t etm_base;\n+ /* Base address of L2 configuration space */\n+ uint32_t l2cfg_base;\n+ uint32_t reserved1;\n+ /* Base address of L1S */\n+ uint32_t l1s0_base;\n+ /* Base address of AXI2 */\n+ uint32_t axi2_lowaddr;\n+ /* Base address of streamer base */\n+ uint32_t streamer_base;\n+ uint32_t reserved2;\n+ /* Base address of fast L2VIC */\n+ uint32_t fastl2vic_base;\n+ /* Number of entries in JTLB */\n+ uint32_t jtlb_size_entries;\n+ /* Coprocessor type */\n+ uint32_t coproc_present;\n+ /* Number of extension execution contexts available */\n+ uint32_t ext_contexts;\n+ /* Base address of Hexagon Vector Tightly Coupled Memory (VTCM) */\n+ uint32_t vtcm_base;\n+ /* Size of VTCM (in KB) */\n+ uint32_t vtcm_size_kb;\n+ /* L2 tag size */\n+ uint32_t l2tag_size;\n+ /* Amount of physical L2 memory in released version */\n+ uint32_t l2ecomem_size;\n+ /* Hardware threads available on the core */\n+ uint32_t thread_enable_mask;\n+ /* Base address of the ECC registers */\n+ uint32_t eccreg_base;\n+ /* L2 line size */\n+ uint32_t l2line_size;\n+ /* Small Core processor (also implies audio extension) */\n+ uint32_t tiny_core;\n+ /* Size of L2TCM */\n+ uint32_t l2itcm_size;\n+ /* Base address of L2-ITCM */\n+ uint32_t l2itcm_base;\n+ uint32_t reserved3;\n+ /* DTM is present */\n+ uint32_t dtm_present;\n+ /* Version of the DMA */\n+ uint32_t dma_version;\n+ /* Native HVX vector length in log of bytes */\n+ uint32_t hvx_vec_log_length;\n+ /* Core ID of the multi-core */\n+ uint32_t core_id;\n+ /* Number of multi-core cores */\n+ uint32_t core_count;\n+ uint32_t coproc2_reg0;\n+ uint32_t coproc2_reg1;\n+ /* Supported HVX vector length */\n+ uint32_t v2x_mode;\n+ uint32_t coproc2_reg2;\n+ uint32_t coproc2_reg3;\n+ uint32_t coproc2_reg4;\n+ uint32_t coproc2_reg5;\n+ uint32_t coproc2_reg6;\n+ uint32_t coproc2_reg7;\n+ /* Voltage droop mitigation technique parameter */\n+ uint32_t acd_preset;\n+ /* Voltage droop mitigation technique parameter */\n+ uint32_t mnd_preset;\n+ /* L1 data cache size (in KB) */\n+ uint32_t l1d_size_kb;\n+ /* L1 instruction cache size in (KB) */\n+ uint32_t l1i_size_kb;\n+ /* L1 data cache write policy: see HexagonL1WritePolicy */\n+ uint32_t l1d_write_policy;\n+ /* VTCM bank width */\n+ uint32_t vtcm_bank_width;\n+ uint32_t reserved4;\n+ uint32_t reserved5;\n+ uint32_t reserved6;\n+ uint32_t coproc2_cvt_mpy_size;\n+ uint32_t consistency_domain;\n+ uint32_t capacity_domain;\n+ uint32_t axi3_lowaddr;\n+ uint32_t coproc2_int8_subcolumns;\n+ uint32_t corecfg_present;\n+ uint32_t coproc2_fp16_acc_exp;\n+ uint32_t AXIM2_secondary_base;\n+ };\n+ uint32_t raw[HEXAGON_CFGSPACE_ENTRIES];\n+};\n+\n+struct hexagon_machine_config {\n+ /* Base address of config table */\n+ uint32_t cfgbase;\n+ /* Size of L2 TCM */\n+ uint32_t l2tcm_size;\n+ /* Base address of L2VIC */\n+ uint32_t l2vic_base;\n+ /* Size of L2VIC region */\n+ uint32_t l2vic_size;\n+ /* QTimer csr base */\n+ uint32_t csr_base;\n+ uint32_t qtmr_region;\n+ union hexagon_config_table cfgtable;\n+};\n+\n+#endif\ndiff --git a/hw/hexagon/machine_cfg_v66g_1024.h.inc b/hw/hexagon/machine_cfg_v66g_1024.h.inc\nnew file mode 100644\nindex 00000000000..cc4d89b89c9\n--- /dev/null\n+++ b/hw/hexagon/machine_cfg_v66g_1024.h.inc\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+static const struct hexagon_machine_config v66g_1024 = {\n+ .cfgbase = 0xd8180000,\n+ .l2tcm_size = 0x00000000,\n+ .l2vic_base = 0xfc910000,\n+ .l2vic_size = 0x00001000,\n+ .csr_base = 0xfc900000,\n+ .qtmr_region = 0xfc921000,\n+ .cfgtable = {\n+ .l2tcm_base = 0x0000d800,\n+ .reserved0 = 0x0000d400,\n+ .subsystem_base = 0x0000fc90,\n+ .etm_base = 0x0000d805,\n+ .l2cfg_base = 0x0000d81a,\n+ .reserved1 = 0x00000000,\n+ .l1s0_base = 0x0000d820,\n+ .axi2_lowaddr = 0x00003000,\n+ .streamer_base = 0x00000000,\n+ .reserved2 = 0x0000d819,\n+ .fastl2vic_base = 0x0000d81e,\n+ .jtlb_size_entries = 0x00000080,\n+ .coproc_present = 0x00000001,\n+ .ext_contexts = 0x00000004,\n+ .vtcm_base = 0x0000d820,\n+ .vtcm_size_kb = 0x00000100,\n+ .l2tag_size = 0x00000400,\n+ .l2ecomem_size = 0x00000400,\n+ .thread_enable_mask = 0x0000000f,\n+ .eccreg_base = 0x0000d81f,\n+ .l2line_size = 0x00000080,\n+ .tiny_core = 0x00000000,\n+ .l2itcm_size = 0x00000000,\n+ .l2itcm_base = 0x0000d820,\n+ .reserved3 = 0x00000000,\n+ .dtm_present = 0x00000000,\n+ .dma_version = 0x00000000,\n+ .hvx_vec_log_length = 0x00000080,\n+ .core_id = 0x00000000,\n+ .core_count = 0x00000000,\n+ .coproc2_reg0 = 0x00000000,\n+ .coproc2_reg1 = 0x00000000,\n+ .v2x_mode = 0x00000000,\n+ .coproc2_reg2 = 0x00000000,\n+ .coproc2_reg3 = 0x00000000,\n+ .coproc2_reg4 = 0x00000000,\n+ .coproc2_reg5 = 0x00000000,\n+ .coproc2_reg6 = 0x00000000,\n+ .coproc2_reg7 = 0x00000000,\n+ .acd_preset = 0x00000000,\n+ .mnd_preset = 0x00000000,\n+ .l1d_size_kb = 0x00000000,\n+ .l1i_size_kb = 0x00000000,\n+ .l1d_write_policy = 0x00000000,\n+ .vtcm_bank_width = 0x00000000,\n+ .reserved4 = 0x00000000,\n+ .reserved5 = 0x00000000,\n+ .reserved6 = 0x00000000,\n+ .coproc2_cvt_mpy_size = 0x00000000,\n+ .consistency_domain = 0x00000000,\n+ .capacity_domain = 0x00000000,\n+ .axi3_lowaddr = 0x00000000,\n+ },\n+};\ndiff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c\nnew file mode 100644\nindex 00000000000..d5df87605f4\n--- /dev/null\n+++ b/hw/hexagon/hexagon_dsp.c\n@@ -0,0 +1,161 @@\n+/*\n+ * Hexagon DSP Subsystem emulation. This represents a generic DSP\n+ * subsystem with few peripherals, like the Compute DSP.\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/units.h\"\n+#include \"system/address-spaces.h\"\n+#include \"hw/core/boards.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"hw/hexagon/hexagon.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+#include \"hw/core/loader.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qemu/log.h\"\n+#include \"elf.h\"\n+#include \"cpu.h\"\n+#include \"migration/cpu.h\"\n+#include \"system/system.h\"\n+#include \"target/hexagon/internal.h\"\n+#include \"system/reset.h\"\n+\n+#include \"machine_cfg_v66g_1024.h.inc\"\n+\n+static void hex_symbol_callback(const char *st_name, int st_info,\n+ uint64_t st_value, uint64_t st_size)\n+{\n+}\n+\n+/* Board init. */\n+static struct hexagon_board_boot_info hexagon_binfo;\n+\n+static void hexagon_load_kernel(HexagonCPU *cpu)\n+{\n+ uint64_t pentry;\n+ long kernel_size;\n+\n+ kernel_size = load_elf_ram_sym(hexagon_binfo.kernel_filename, NULL, NULL,\n+ NULL, &pentry, NULL, NULL,\n+ &hexagon_binfo.kernel_elf_flags, 0, EM_HEXAGON, 0, 0,\n+ &address_space_memory, false, hex_symbol_callback);\n+\n+ if (kernel_size <= 0) {\n+ error_report(\"no kernel file '%s'\",\n+ hexagon_binfo.kernel_filename);\n+ exit(1);\n+ }\n+\n+ qdev_prop_set_uint32(DEVICE(cpu), \"exec-start-addr\", pentry);\n+}\n+\n+static void hexagon_init_bootstrap(MachineState *machine, HexagonCPU *cpu)\n+{\n+ if (machine->kernel_filename) {\n+ hexagon_load_kernel(cpu);\n+ }\n+}\n+\n+static void do_cpu_reset(void *opaque)\n+{\n+ HexagonCPU *cpu = opaque;\n+ CPUState *cs = CPU(cpu);\n+ cpu_reset(cs);\n+}\n+\n+static void hexagon_common_init(MachineState *machine, Rev_t rev,\n+ const struct hexagon_machine_config *m_cfg)\n+{\n+ MemoryRegion *address_space;\n+ MemoryRegion *sram;\n+ DeviceState *glob_regs_dev;\n+\n+ memset(&hexagon_binfo, 0, sizeof(hexagon_binfo));\n+ if (machine->kernel_filename) {\n+ hexagon_binfo.ram_size = machine->ram_size;\n+ hexagon_binfo.kernel_filename = machine->kernel_filename;\n+ }\n+\n+ machine->enable_graphics = 0;\n+\n+ address_space = get_system_memory();\n+\n+ sram = g_new(MemoryRegion, 1);\n+ memory_region_init_ram(sram, NULL, \"ddr.ram\",\n+ machine->ram_size, &error_fatal);\n+ memory_region_add_subregion(address_space, 0x0, sram);\n+\n+ glob_regs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);\n+ qdev_prop_set_uint64(glob_regs_dev, \"config-table-addr\", m_cfg->cfgbase);\n+ sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal);\n+\n+ for (int i = 0; i < machine->smp.cpus; i++) {\n+ HexagonCPU *cpu = HEXAGON_CPU(object_new(machine->cpu_type));\n+ qemu_register_reset(do_cpu_reset, cpu);\n+\n+ /*\n+ * CPU #0 is the only CPU running at boot, others must be\n+ * explicitly enabled via start instruction.\n+ */\n+ qdev_prop_set_bit(DEVICE(cpu), \"start-powered-off\", (i != 0));\n+ if (i == 0) {\n+ hexagon_init_bootstrap(machine, cpu);\n+ if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) {\n+ return;\n+ }\n+ } else if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) {\n+ return;\n+ }\n+\n+ }\n+}\n+\n+static void init_mc(MachineClass *mc)\n+{\n+ mc->block_default_type = IF_SD;\n+ mc->default_ram_size = 4 * GiB;\n+ mc->no_parallel = 1;\n+ mc->no_floppy = 1;\n+ mc->no_cdrom = 1;\n+ mc->no_serial = 1;\n+ mc->is_default = false;\n+ mc->max_cpus = 8;\n+}\n+\n+/* ----------------------------------------------------------------- */\n+/* Core-specific configuration settings are defined below this line. */\n+/* Config table values defined in machine_configs.h.inc */\n+/* ----------------------------------------------------------------- */\n+\n+static void v66g_1024_config_init(MachineState *machine)\n+{\n+ hexagon_common_init(machine, v66_rev, &v66g_1024);\n+}\n+\n+static void v66g_1024_init(ObjectClass *oc, const void *data)\n+{\n+ MachineClass *mc = MACHINE_CLASS(oc);\n+\n+ mc->desc = \"Hexagon V66G_1024\";\n+ mc->init = v66g_1024_config_init;\n+ init_mc(mc);\n+ mc->is_default = true;\n+ mc->default_cpu_type = TYPE_HEXAGON_CPU_V66;\n+ mc->default_cpus = 4;\n+}\n+\n+static const TypeInfo hexagon_machine_types[] = {\n+ {\n+ .name = MACHINE_TYPE_NAME(\"V66G_1024\"),\n+ .parent = TYPE_MACHINE,\n+ .class_init = v66g_1024_init,\n+ },\n+};\n+\n+DEFINE_TYPES(hexagon_machine_types)\ndiff --git a/system/qdev-monitor.c b/system/qdev-monitor.c\nindex 1ac6d9a8575..72abc9182a9 100644\n--- a/system/qdev-monitor.c\n+++ b/system/qdev-monitor.c\n@@ -69,7 +69,7 @@ typedef struct QDevAlias\n QEMU_ARCH_SPARC | \\\n QEMU_ARCH_XTENSA)\n #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)\n-#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)\n+#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K | QEMU_ARCH_HEXAGON)\n \n /* Please keep this table sorted by typename. */\n static const QDevAlias qdev_alias_table[] = {\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex ae980c087f0..15258a203b3 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -32,6 +32,7 @@\n #include \"translate.h\"\n #include \"genptr.h\"\n #include \"printinsn.h\"\n+#include \"exec/target_page.h\"\n \n #define HELPER_H \"helper.h\"\n #include \"exec/helper-info.c.inc\"\ndiff --git a/hw/Kconfig b/hw/Kconfig\nindex b3ed092f7a8..dda3139be74 100644\n--- a/hw/Kconfig\n+++ b/hw/Kconfig\n@@ -54,6 +54,7 @@ source arm/Kconfig\n source cpu/Kconfig\n source alpha/Kconfig\n source avr/Kconfig\n+source hexagon/Kconfig\n source hppa/Kconfig\n source i386/Kconfig\n source loongarch/Kconfig\ndiff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig\nnew file mode 100644\nindex 00000000000..7b9577f68f7\n--- /dev/null\n+++ b/hw/hexagon/Kconfig\n@@ -0,0 +1,5 @@\n+config HEX_DSP\n+ bool\n+ default y\n+ depends on HEXAGON && TCG\n+ imply PTIMER\ndiff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build\nnew file mode 100644\nindex 00000000000..f528d2bc4ab\n--- /dev/null\n+++ b/hw/hexagon/meson.build\n@@ -0,0 +1,6 @@\n+hexagon_ss = ss.source_set()\n+hexagon_ss.add(files('hexagon_tlb.c'))\n+hexagon_ss.add(files('hexagon_globalreg.c'))\n+hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c'))\n+\n+hw_arch += {'hexagon': hexagon_ss}\ndiff --git a/hw/meson.build b/hw/meson.build\nindex ef65ba51950..7fa81db453e 100644\n--- a/hw/meson.build\n+++ b/hw/meson.build\n@@ -3,6 +3,7 @@ subdir('alpha')\n subdir('arm')\n subdir('avr')\n subdir('hppa')\n+subdir('hexagon')\n subdir('xenpv') # i386 uses it\n subdir('i386')\n subdir('loongarch')\n", "prefixes": [ "v4", "3/9" ] }