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GET /api/1.1/patches/2220974/?format=api
{ "id": 2220974, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220974/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260408-hawi-pinctrl-v2-1-fd7f681f5e05@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408-hawi-pinctrl-v2-1-fd7f681f5e05@oss.qualcomm.com>", "date": "2026-04-08T14:15:47", "name": "[v2,1/2] dt-bindings: pinctrl: qcom: Describe Hawi TLMM block", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b7cbaef1fdadbaac5b35bb465c5bb3a26fbe1f0c", "submitter": { "id": 89980, "url": "http://patchwork.ozlabs.org/api/1.1/people/89980/?format=api", "name": "Mukesh Ojha", "email": "mukesh.ojha@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260408-hawi-pinctrl-v2-1-fd7f681f5e05@oss.qualcomm.com/mbox/", "series": [ { "id": 499149, "url": "http://patchwork.ozlabs.org/api/1.1/series/499149/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499149", "date": "2026-04-08T14:15:47", "name": "pinctrl: qcom: Introduce Pinctrl for Hawi SoC", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499149/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220974/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220974/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-34888-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UPk1ErUq;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=TTRuX8ie;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260408-hawi-pinctrl-v2-1-fd7f681f5e05@oss.qualcomm.com>", "References": "<20260408-hawi-pinctrl-v2-0-fd7f681f5e05@oss.qualcomm.com>", "In-Reply-To": "<20260408-hawi-pinctrl-v2-0-fd7f681f5e05@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org", "X-Mailer": "b4 0.14-dev-f7c49", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775657757; l=4827;\n i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id;\n bh=kHzuLPUltd0bXrolfSiSxBpD8dRl1Wvbyu0ExBHkXN8=;\n b=Jnu4jyweO2IZniw/0pJz6wkk1iFmztPrXFsCJHhbkgbsgJ5hs8JRuJdmSVhab2SkklEhM8CXJ\n 9+CdKyMDMiODroP033Ta9g3+NSSfkeI8bE4V2Ahb2iyTAtr5XhVkH1b", "X-Developer-Key": "i=mukesh.ojha@oss.qualcomm.com; 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Hawi TLMM block\n+\n+maintainers:\n+ - Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>\n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,hawi-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 113\n+\n+ gpio-line-names:\n+ maxItems: 226\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-hawi-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-hawi-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-hawi-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$\"\n+ - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+ enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,\n+ audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,\n+ cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,\n+ coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,\n+ dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,\n+ i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,\n+ ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,\n+ mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,\n+ mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,\n+ modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,\n+ nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,\n+ phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,\n+ qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,\n+ qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,\n+ qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,\n+ qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,\n+ qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,\n+ qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,\n+ rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,\n+ sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,\n+ uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,\n+ wcn_sw_ctrl ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@f100000 {\n+ compatible = \"qcom,hawi-tlmm\";\n+ reg = <0x0f100000 0x300000>;\n+ interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 227>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ qup-uart7-state {\n+ pins = \"gpio62\", \"gpio63\";\n+ function = \"qup1_se7\";\n+ };\n+ };\n+...\n", "prefixes": [ "v2", "1/2" ] }