[{"id":3675134,"web_url":"http://patchwork.ozlabs.org/comment/3675134/","msgid":"<20260409-chestnut-mink-of-election-9e8a9d@quoll>","list_archive_url":null,"date":"2026-04-09T07:59:05","subject":"Re: [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Describe Hawi TLMM\n block","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Wed, Apr 08, 2026 at 07:45:47PM +0530, Mukesh Ojha wrote:\n> The Top Level Mode Multiplexer (TLMM) in the Qualcomm Hawi SoC\n> provides GPIO and pinctrl functionality for UFS, SDC and 226\n> GPIO pins.\n> \n> Add a DeviceTree binding to describe the TLMM block on Qualcomm's\n> Hawi SoC.\n> \n> Signed-off-by: Mukesh Ojha \n> ---\n> .../bindings/pinctrl/qcom,hawi-tlmm.yaml | 120 +++++++++++++++++++++\n> 1 file changed, 120 insertions(+)\n\nReviewed-by: Krzysztof Kozlowski \n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=gGNKpipl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260408-hawi-pinctrl-v2-1-fd7f681f5e05@oss.qualcomm.com>"}}]