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GET /api/1.1/patches/2220774/?format=api
{ "id": 2220774, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220774/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260408025243.1155482-3-eleanor.lin@realtek.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408025243.1155482-3-eleanor.lin@realtek.com>", "date": "2026-04-08T02:52:41", "name": "[v2,2/4] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e0b8363df42f410e69d9c54bbf95c0e63251dbc1", "submitter": { "id": 92797, "url": "http://patchwork.ozlabs.org/api/1.1/people/92797/?format=api", "name": "Yu-Chun Lin [林祐君]", "email": "eleanor.lin@realtek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260408025243.1155482-3-eleanor.lin@realtek.com/mbox/", "series": [ { "id": 499060, "url": "http://patchwork.ozlabs.org/api/1.1/series/499060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499060", "date": "2026-04-08T02:52:40", "name": "gpio: realtek: Add support for Realtek DHC RTD1625", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499060/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220774/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220774/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-34854-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=realtek.com header.i=@realtek.com header.a=rsa-sha256\n header.s=dkim header.b=r67pmIvF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34854-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com\n header.b=\"r67pmIvF\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=211.75.126.72", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=realtek.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=realtek.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fr73p4TRFz1yD6\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 12:55:50 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id D9456300B5A3\n\tfor <incoming@patchwork.ozlabs.org>; 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Wed, 8 Apr 2026 10:52:45 +0800", "from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw\n (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Wed, 8 Apr 2026 10:52:45 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775616942; cv=none;\n b=ffVnDBcy8nMomWfdvBW4Zk45gZGFOUN3D1KvKh+wvRCyd+JPF9+L1quBQfHvKUxCCRlerfkqIaQ7poc/IU4tvU/kUK5h90mhb/AsE0Crhpaho8WvvBuN903N4J8FKzElMrlpmcAJeH5E4Mj8Y6aq2+rktzBVNGdYtgrmLQNOVzc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775616942; c=relaxed/simple;\n\tbh=0c/zh9AL9+FKEmJBDPRVLWMCvnzS5SzgjfQcEgpQHOk=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=II3oj+ppF/yk/gbJNTh+ja/47CX1iszxU9t4bcYWddAspNfNkK0ivWcqZdLCMq8BCMyybgkCU25WlBGgzquvAhEjcomC8xek6ZlPUitHdWbGIJM8Ygy/MOnCiAhPU3mq9UoX9c1qHZ8Z+Do7+2iBmE2mPLct9WAQp7m3yGwaPC4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=realtek.com;\n spf=pass smtp.mailfrom=realtek.com;\n dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com\n header.b=r67pmIvF; arc=none smtp.client-ip=211.75.126.72", "X-SpamFilter-By": "ArmorX SpamTrap 5.80 with qID 6382qkBcB2349159,\n This message is accepted by code: ctloc85258", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim;\n\tt=1775616766; bh=swGybb+9llsVg/eIQciZTiYrsdseWcN8ezhyU/fBs9k=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Transfer-Encoding:Content-Type;\n\tb=r67pmIvFfWZGBZ6/hTkhiLRUlTp4Spt0kNxBRcR+2ojCyeQoW47JNlg3w2X+e2snR\n\t sQnYVhvsecUEkYSzyOm9NJdCQ8N5vM2eS+UdkSn/sI1tQgABJO8v33RvO3R04bSBLq\n\t qIkhHUMtqvmNY8gY1HnJ8Eu/rLcSeWfNVAfSTV/QG1G2PWJHMZVuQrQz9aXvuvibmE\n\t euYhcET2XCJlGk3L5Pg8AAIB4q/zKhpgUEdZXlem+YjYcPkIR8Cwu0EnG6op6V5/Mh\n\t aLgVYhJFgl+Qovmkfsj62GJHhw8R7A9jMZ/7auEHaJSBF/3lpdDmnKvdJs25MPHTNV\n\t aP2yBhPem60Mw==", "From": "Yu-Chun Lin <eleanor.lin@realtek.com>", "To": "<linusw@kernel.org>, <brgl@kernel.org>, <robh@kernel.org>,\n <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <afaerber@suse.com>,\n <tychang@realtek.com>", "CC": "<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-realtek-soc@lists.infradead.org>, <cy.huang@realtek.com>,\n <stanley_chang@realtek.com>, <eleanor.lin@realtek.com>,\n <james.tai@realtek.com>", "Subject": "[PATCH v2 2/4] dt-bindings: gpio: realtek: Add realtek,rtd1625-gpio", "Date": "Wed, 8 Apr 2026 10:52:41 +0800", "Message-ID": "<20260408025243.1155482-3-eleanor.lin@realtek.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260408025243.1155482-1-eleanor.lin@realtek.com>", "References": "<20260408025243.1155482-1-eleanor.lin@realtek.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain" }, "content": "From: Tzuyi Chang <tychang@realtek.com>\n\nAdd the device tree bindings for the Realtek DHC (Digital Home Center)\nRTD1625 GPIO controllers.\n\nThe RTD1625 GPIO controller features a per-pin register architecture\nthat differs significantly from previous generations. It utilizes\nseparate register blocks for GPIO configuration and interrupt control.\n\nSigned-off-by: Tzuyi Chang <tychang@realtek.com>\nSigned-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>\n---\nChanges in v2:\n- Merge two memory regions into one.\n- Add a description for the reg region.\n---\n .../bindings/gpio/realtek,rtd1625-gpio.yaml | 82 +++++++++++++++++++\n 1 file changed, 82 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml\nnew file mode 100644\nindex 000000000000..de873876b8c6\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml\n@@ -0,0 +1,82 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+# Copyright 2023 Realtek Semiconductor Corporation\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek DHC RTD1625 GPIO controller\n+\n+maintainers:\n+ - Tzuyi Chang <tychang@realtek.com>\n+\n+description: |\n+ GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register\n+ architecture that differs significantly from earlier RTD series controllers.\n+ Each GPIO has dedicated registers for configuration (direction, input/output\n+ values, debounce), and interrupt control supporting edge and level detection\n+ modes.\n+\n+properties:\n+ compatible:\n+ enum:\n+ - realtek,rtd1625-iso-gpio\n+ - realtek,rtd1625-isom-gpio\n+\n+ reg:\n+ maxItems: 1\n+ description: |\n+ Memory region containing both interrupt control and GPIO\n+ configuration registers in a contiguous address space.\n+\n+ For realtek,rtd1625-iso-gpio:\n+ - Base + 0x0 ~ 0xff: Interrupt control registers\n+ - Base + 0x100 ~ 0x397: GPIO configuration registers\n+\n+ For realtek,rtd1625-isom-gpio:\n+ - Base + 0x0 ~ 0x1f: Interrupt control registers\n+ - Base + 0x20 ~ 0x2f: GPIO configuration registers\n+\n+ interrupts:\n+ items:\n+ - description: Interrupt number of the assert GPIO interrupt, which is\n+ triggered when there is a rising edge.\n+ - description: Interrupt number of the deassert GPIO interrupt, which is\n+ triggered when there is a falling edge.\n+ - description: Interrupt number of the level-sensitive GPIO interrupt,\n+ triggered by a configured logic level.\n+\n+ interrupt-controller: true\n+\n+ \"#interrupt-cells\":\n+ const: 2\n+\n+ gpio-ranges: true\n+\n+ gpio-controller: true\n+\n+ \"#gpio-cells\":\n+ const: 2\n+\n+required:\n+ - compatible\n+ - reg\n+ - gpio-ranges\n+ - gpio-controller\n+ - \"#gpio-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ gpio@89100 {\n+ compatible = \"realtek,rtd1625-isom-gpio\";\n+ reg = <0x89100 0x30>;\n+ interrupt-parent = <&iso_m_irq_mux>;\n+ interrupts = <0>, <1>, <2>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-ranges = <&isom_pinctrl 0 0 4>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ };\n", "prefixes": [ "v2", "2/4" ] }