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GET /api/1.1/patches/2220367/?format=api
{ "id": 2220367, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com>", "date": "2026-04-07T02:40:54", "name": "[v2,3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ae03f934d8e3b763459e46032af0b13bef4d0147", "submitter": { "id": 92886, "url": "http://patchwork.ozlabs.org/api/1.1/people/92886/?format=api", "name": "Jia Wang", "email": "wangjia@ultrarisc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com/mbox/", "series": [ { "id": 498910, "url": "http://patchwork.ozlabs.org/api/1.1/series/498910/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498910", "date": "2026-04-07T02:40:55", "name": "riscv: Add PCIe support for UltraRISC DP1000 SoC", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498910/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220367/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-51986-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=Fb1gbpfZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=ultrarisc.com;\n spf=none smtp.mailfrom=ultrarisc.com;\n dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.b=Fb1gbpfZ; arc=none smtp.client-ip=218.76.62.146", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=ultrarisc.com; s=dkim; h=Received:From:Date:Subject:\n\tMIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:\n\tReferences:In-Reply-To:To:Cc; bh=zxY1VY+lBxzA0Zky0PLENhVVOAkvhGt\n\tyiMmOwdRciS4=; b=Fb1gbpfZ1PbdzGypBGkkuLkU8IFImjxgjCa7fP9BiDRaf9u\n\tV1i/GAq857YJ/nCedXZ/3mh8daCWiVzbxFsW5cN1XttLX1JT4jVSi3hUAe1JgUr/\n\t3wojOV3YhYCaS7ynCVuZkUZcKFzlP0VlLqn9TtUx5CY1AVGsjK3E9L+67KrU=", "From": "Jia Wang <wangjia@ultrarisc.com>", "Date": "Tue, 07 Apr 2026 10:40:54 +0800", "Subject": "[PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com>", "References": "<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>", "In-Reply-To": "<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n Xincheng Zhang <zhangxincheng@ultrarisc.com>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang <wangjia@ultrarisc.com>", "X-Mailer": "b4 0.15-dev", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775529665; l=3584;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=n6k/8wVJxmWBeO9BePZHpNqxXLjgjCXk7EWhwiY8EOc=;\n b=4U9tay0snX893PxYeDI0ZtUoKjuXL9cGomfwis8ZKod2+9hoZwf3QZ4OiXHovJkU91RsSoM9B\n PF7UtjO9w8gDECWOyaFrErsZwUPF0xTyjBKlWU7xOW+IasOav+Fp3oS", "X-Developer-Key": "i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=", "X-CM-TRANSID": "AQAAfwDXEELwbtRpBZsBAA--.862S5", "X-Coremail-Antispam": "1UD129KBjvJXoWxZw4kZr4UtrW7GrWktFWxtFb_yoW5ZryfpF\n\tW5Ca4kCF4xtr13uw4fG3W0kF15JF4vkFZYkwnFgw43JrZYgFWjqrsIkw43Jw15GrWDXw12\n\tgFn0v347Kw17Aw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnRJUUUmG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n\trVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2\n\tx26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0\n\tY4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2\n\t8EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS\n\t0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2\n\tIY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0\n\tY48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2\n\txKxwCY1x0262kKe7AKxVW8ZVWrXwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E\n\t4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGV\n\tWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_\n\tJr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj4\n\t0_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8\n\tJrUvcSsGvfC2KfnxnUUI43ZEXa7VUUbAw7UUUUU==", "X-CM-SenderInfo": "pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnTLbsAJAAAsS" }, "content": "Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.\n\nSigned-off-by: Jia Wang <wangjia@ultrarisc.com>\n---\n .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 103 +++++++++++++++++++++\n 1 file changed, 103 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\nnew file mode 100644\nindex 000000000000..d0517130e127\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n@@ -0,0 +1,103 @@\n+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: UltraRISC DP1000 PCIe Host Controller\n+\n+description: |\n+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.\n+ This binding describes the UltraRISC specific extensions to the base\n+ DesignWare PCIe binding.\n+\n+maintainers:\n+ - Xincheng Zhang <zhangxincheng@ultrarisc.com>\n+ - Jia Wang <wangjia@ultrarisc.com>\n+\n+allOf:\n+ - $ref: /schemas/pci/snps,dw-pcie.yaml#\n+\n+properties:\n+ compatible:\n+ const: ultrarisc,dp1000-pcie\n+\n+ reg:\n+ items:\n+ - description: Data Bus Interface (DBI) registers.\n+ - description: PCIe configuration space region.\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: config\n+\n+ num-lanes:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ enum: [4, 16]\n+ description: Number of lanes to use.\n+\n+ max-link-speed:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ const: 4\n+ description: Maximum PCIe link speed supported.\n+\n+ interrupts:\n+ description: List of interrupt specifiers used by the controller\n+ items:\n+ - description: MSI interrupt\n+ - description: Legacy INTA interrupt\n+ - description: Legacy INTB interrupt\n+ - description: Legacy INTC interrupt\n+ - description: Legacy INTD interrupt\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+ - const: inta\n+ - const: intb\n+ - const: intc\n+ - const: intd\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - interrupts\n+ - interrupt-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie_x16: pcie@21000000 {\n+ compatible = \"ultrarisc,dp1000-pcie\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ #interrupt-cells = <1>;\n+ reg = <0x0 0x21000000 0x0 0x01000000>,\n+ <0x0 0x4fff0000 0x0 0x00010000>;\n+ reg-names = \"dbi\", \"config\";\n+ device_type = \"pci\";\n+ dma-coherent;\n+ bus-range = <0x0 0xff>;\n+ num-lanes = <16>;\n+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,\n+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,\n+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;\n+\n+ max-link-speed = <4>;\n+ interrupt-parent = <&plic>;\n+ interrupts = <43>, <44>, <45>, <46>, <47>;\n+ interrupt-names = \"msi\", \"inta\", \"intb\", \"intc\", \"intd\";\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,\n+ <0x0 0x0 0x0 0x2 &plic 45>,\n+ <0x0 0x0 0x0 0x3 &plic 46>,\n+ <0x0 0x0 0x0 0x4 &plic 47>;\n+ };\n+ };\n", "prefixes": [ "v2", "3/4" ] }