[{"id":3673987,"web_url":"http://patchwork.ozlabs.org/comment/3673987/","msgid":"<20260407-uptight-tody-of-weather-ae1e35@quoll>","list_archive_url":null,"date":"2026-04-07T07:50:41","subject":"Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Tue, Apr 07, 2026 at 10:40:54AM +0800, Jia Wang wrote:\n> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.\n> \n> Signed-off-by: Jia Wang \n> ---\n> .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 103 +++++++++++++++++++++\n> 1 file changed, 103 insertions(+)\n> \n> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n> new file mode 100644\n> index 000000000000..d0517130e127\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n> @@ -0,0 +1,103 @@\n> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n> +%YAML 1.2\n> +---\n> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#\n> +$schema: http://devicetree.org/meta-schemas/core.yaml#\n> +\n> +title: UltraRISC DP1000 PCIe Host Controller\n> +\n> +description: |\n\nDo not need '|' unless you need to preserve formatting.\n\n> + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.\n> + This binding describes the UltraRISC specific extensions to the base\n> + DesignWare PCIe binding.\n\nDrop sentence. Do not describe in description what the binding\ndescribes. It's circular / repetitive. Just describe that.\n\n> +\n> +maintainers:\n> + - Xincheng Zhang \n> + - Jia Wang \n> +\n> +allOf:\n> + - $ref: /schemas/pci/snps,dw-pcie.yaml#\n> +\n> +properties:\n> + compatible:\n> + const: ultrarisc,dp1000-pcie\n> +\n> + reg:\n> + items:\n> + - description: Data Bus Interface (DBI) registers.\n> + - description: PCIe configuration space region.\n> +\n> + reg-names:\n> + items:\n> + - const: dbi\n> + - const: config\n> +\n> + num-lanes:\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + enum: [4, 16]\n> + description: Number of lanes to use.\n> +\n> + max-link-speed:\n> + $ref: /schemas/types.yaml#/definitions/uint32\n> + const: 4\n\nIf const then deducible from the compatible. Drop the property.\n\n> + description: Maximum PCIe link speed supported.\n> +\n> + interrupts:\n> + description: List of interrupt specifiers used by the controller\n\nDrop description. Obvious.\n\n> + items:\n> + - description: MSI interrupt\n> + - description: Legacy INTA interrupt\n> + - description: Legacy INTB interrupt\n> + - description: Legacy INTC interrupt\n> + - description: Legacy INTD interrupt\n> +\n> + interrupt-names:\n> + items:\n> + - const: msi\n> + - const: inta\n> + - const: intb\n> + - const: intc\n> + - const: intd\n> +\n> +required:\n> + - compatible\n> + - reg\n> + - reg-names\n> + - interrupts\n> + - interrupt-names\n> +\n> +unevaluatedProperties: false\n> +\n> +examples:\n> + - |\n> + soc {\n> + #address-cells = <2>;\n> + #size-cells = <2>;\n> +\n> + pcie_x16: pcie@21000000 {\n\nDrop unused label\n\n> + compatible = \"ultrarisc,dp1000-pcie\";\n\nreg, names and ranges go here. Please follow DTS coding style.\n\n> + #address-cells = <3>;\n> + #size-cells = <2>;\n> + #interrupt-cells = <1>;\n> + reg = <0x0 0x21000000 0x0 0x01000000>,\n> + <0x0 0x4fff0000 0x0 0x00010000>;\n> + reg-names = \"dbi\", \"config\";\n> + device_type = \"pci\";\n> + dma-coherent;\n> + bus-range = <0x0 0xff>;\n> + num-lanes = <16>;\n> + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,\n> + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,\n> + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;\n> +\n> + max-link-speed = <4>;\n\nDrop, compatible defines this.\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=oPXw++5u;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775548244; cv=none;\n b=apeULu1j7mkTn9G4xJlJhgdtA1PHuZgMdwHbpO97z17qis9S8Y7n4+a9Shv5CgMLD/FI9tVx92pnT8KpG5moGqj/kqgFipnmUHyf44V/PyMYQW8Y3sHJxDsud4bi01Eg3prNJv4TdxzYQsppjKFXzlWqfKbdcI4/9hZqCrcRHT8=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775548244; c=relaxed/simple;\n\tbh=V9L0KgtiKRhBAbkYtOsVEM62GU0dI0FGYEnsgKtc70Y=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=f7wHnmSc/ZvGdBcIHIaOQfqgnYJ+hACgqu+uITzcYCbS+XqovOKjmBgutDECXgxrev2nL40FwAKVxrp25fwttRF31mp8yEnxFF6ohaVOFssGY7w1DpKCb9bmQpxJV1mS7fYpNEoZF8f2QlwW3a6h+pVq+GqCmRxNh0VKrUafqXQ=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=oPXw++5u; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775548243;\n\tbh=V9L0KgtiKRhBAbkYtOsVEM62GU0dI0FGYEnsgKtc70Y=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=oPXw++5uE3nR3/HNEy5uVeVDsAFaPTiiKKqGHTjB4Rn22ReQsMHvGC/mi78bptaXw\n\t w7SeJfUJy8pui3uEJLY+/QNbZsP8bBvrgvWvCsK42E4lU2+aKLFSS3LAZTWvE+yoLB\n\t aiUFlPUSHLs6ydgC5O6V30QmiHiK5jQOeBeutcouIdNVlzoHD1QHVIieIj/B76z9r1\n\t oGEfUQIlHyvebi3G8m4oOKTKbXJB3l5d0JarBHW9+bHIJWWir+kTIZJX8dVbilx3y8\n\t 4KJmzAFEJpRvi0mIV4d91tejY8s4mfl105Kz/Qqw1IPNo00G+tDNcmt4Cd3QHKkfsz\n\t PC5YzSAe7r93w==","Date":"Tue, 7 Apr 2026 09:50:41 +0200","From":"Krzysztof Kozlowski ","To":"Jia Wang ","Cc":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-riscv@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org","Subject":"Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","Message-ID":"<20260407-uptight-tody-of-weather-ae1e35@quoll>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>\n <20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com>"}},{"id":3674530,"web_url":"http://patchwork.ozlabs.org/comment/3674530/","msgid":"<177561928084.2918127.18218641774926914517.b4-reply@b4>","list_archive_url":null,"date":"2026-04-08T03:34:40","subject":"Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/people/92886/","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"content":"On 2026-04-07 09:50 +0200, Krzysztof Kozlowski wrote:\n> On Tue, Apr 07, 2026 at 10:40:54AM +0800, Jia Wang wrote:\n> > Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.\n> > \n> > Signed-off-by: Jia Wang \n> > ---\n> > .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 103 +++++++++++++++++++++\n> > 1 file changed, 103 insertions(+)\n> > \n> > diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n> > new file mode 100644\n> > index 000000000000..d0517130e127\n> > --- /dev/null\n> > +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml\n> > @@ -0,0 +1,103 @@\n> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n> > +%YAML 1.2\n> > +---\n> > +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#\n> > +$schema: http://devicetree.org/meta-schemas/core.yaml#\n> > +\n> > +title: UltraRISC DP1000 PCIe Host Controller\n> > +\n> > +description: |\n> \n> Do not need '|' unless you need to preserve formatting.\n>\n\nHi Krzysztof,\n\nThanks. I’ll remove the `|` in v3.\n \n> > + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.\n> > + This binding describes the UltraRISC specific extensions to the base\n> > + DesignWare PCIe binding.\n> \n> Drop sentence. Do not describe in description what the binding\n> describes. It's circular / repetitive. Just describe that.\n> \n\nWill simplify the description to a single concise statement in v3.\n\n> > +\n> > +maintainers:\n> > + - Xincheng Zhang \n> > + - Jia Wang \n> > +\n> > +allOf:\n> > + - $ref: /schemas/pci/snps,dw-pcie.yaml#\n> > +\n> > +properties:\n> > + compatible:\n> > + const: ultrarisc,dp1000-pcie\n> > +\n> > + reg:\n> > + items:\n> > + - description: Data Bus Interface (DBI) registers.\n> > + - description: PCIe configuration space region.\n> > +\n> > + reg-names:\n> > + items:\n> > + - const: dbi\n> > + - const: config\n> > +\n> > + num-lanes:\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + enum: [4, 16]\n> > + description: Number of lanes to use.\n> > +\n> > + max-link-speed:\n> > + $ref: /schemas/types.yaml#/definitions/uint32\n> > + const: 4\n> \n> If const then deducible from the compatible. Drop the property.\n> \n\nWill replace `const: 4` with `maximum: 4` in v3.\n\n> > + description: Maximum PCIe link speed supported.\n> > +\n> > + interrupts:\n> > + description: List of interrupt specifiers used by the controller\n> \n> Drop description. Obvious.\n> \n\nWill drop the description in v3.\n\n> > + items:\n> > + - description: MSI interrupt\n> > + - description: Legacy INTA interrupt\n> > + - description: Legacy INTB interrupt\n> > + - description: Legacy INTC interrupt\n> > + - description: Legacy INTD interrupt\n> > +\n> > + interrupt-names:\n> > + items:\n> > + - const: msi\n> > + - const: inta\n> > + - const: intb\n> > + - const: intc\n> > + - const: intd\n> > +\n> > +required:\n> > + - compatible\n> > + - reg\n> > + - reg-names\n> > + - interrupts\n> > + - interrupt-names\n> > +\n> > +unevaluatedProperties: false\n> > +\n> > +examples:\n> > + - |\n> > + soc {\n> > + #address-cells = <2>;\n> > + #size-cells = <2>;\n> > +\n> > + pcie_x16: pcie@21000000 {\n> \n> Drop unused label\n> \n\nWill drop it in v3.\n\n> > + compatible = \"ultrarisc,dp1000-pcie\";\n> \n> reg, names and ranges go here. Please follow DTS coding style.\n> \n\nWill update the example to include reg, reg-names, and ranges following DTS\ncoding style in v3.\n\n> > + #address-cells = <3>;\n> > + #size-cells = <2>;\n> > + #interrupt-cells = <1>;\n> > + reg = <0x0 0x21000000 0x0 0x01000000>,\n> > + <0x0 0x4fff0000 0x0 0x00010000>;\n> > + reg-names = \"dbi\", \"config\";\n> > + device_type = \"pci\";\n> > + dma-coherent;\n> > + bus-range = <0x0 0xff>;\n> > + num-lanes = <16>;\n> > + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,\n> > + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,\n> > + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;\n> > +\n> > + max-link-speed = <4>;\n> \n> Drop, compatible defines this.\n> \n> Best regards,\n> Krzysztof\n> \n> \n\nBest regards,\nJia Wang","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=LVD6ylXG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Drop the property.\n>>\n> \n> Will replace `const: 4` with `maximum: 4` in v3.\n\nWhy? Wasn't maximum link speed fixed to 4?\n\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=rSuiGnoc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52120-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"rSuiGnoc\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frCrK66F1z1xtJ\n\tfor ; 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charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3674585,"web_url":"http://patchwork.ozlabs.org/comment/3674585/","msgid":"<177563059910.3194559.10112671473525736823.b4-reply@b4>","list_archive_url":null,"date":"2026-04-08T06:43:19","subject":"Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/people/92886/","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"content":"On 2026-04-08 08:28 +0200, Krzysztof Kozlowski wrote:\n> On 08/04/2026 05:34, Jia Wang wrote:\n> >>> + max-link-speed:\n> >>> + $ref: /schemas/types.yaml#/definitions/uint32\n> >>> + const: 4\n> >>\n> >> If const then deducible from the compatible. Drop the property.\n> >>\n> > \n> > Will replace `const: 4` with `maximum: 4` in v3.\n> \n> Why? Wasn't maximum link speed fixed to 4?\n>\n\nJust to make sure I fully understand: since the maximum link speed is a\nfixed hardware property and is implied by the compatible, we should drop\nthe `max-link-speed` property from the binding.\n\nIn that case, should I set `pci->max_link_speed = 4` in the driver during\nprobe? I want to make sure this is the correct way to handle it.\n \n> \n> Best regards,\n> Krzysztof\n> \n\nBest regards,\nJia Wang","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=EYx66LlO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-52125-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.b=\"EYx66LlO\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=218.76.62.146","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=ultrarisc.com","smtp.subspace.kernel.org;\n spf=none smtp.mailfrom=ultrarisc.com"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frD6p6L5Pz1xv0\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Subject":"Re: [PATCH v2 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe\n controller","From":"Jia Wang ","To":"Krzysztof Kozlowski ","Cc":"Jia Wang , Paul Walmsley ,\n Palmer Dabbelt , Albert Ou ,\n Alexandre Ghiti , Lorenzo Pieralisi ,\n\t=?utf-8?q?Krzysztof_Wilczy=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley , linux-riscv@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org","In-Reply-To":"<13907c0e-0502-413d-b54d-4e903f5c781e@kernel.org>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>\n <20260407-ultrarisc-pcie-v2-3-2aa2a19a7fb3@ultrarisc.com>\n <20260407-uptight-tody-of-weather-ae1e35@quoll>\n <177561928084.2918127.18218641774926914517.b4-reply@b4>\n <13907c0e-0502-413d-b54d-4e903f5c781e@kernel.org>","Date":"Wed, 08 Apr 2026 14:43:19 +0800","Message-Id":"<177563059910.3194559.10112671473525736823.b4-reply@b4>","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; 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Drop the property.\n>>>>\n>>>\n>>> Will replace `const: 4` with `maximum: 4` in v3.\n>>\n>> Why? Wasn't maximum link speed fixed to 4?\n>>\n> \n> Just to make sure I fully understand: since the maximum link speed is a\n> fixed hardware property and is implied by the compatible, we should drop\n> the `max-link-speed` property from the binding.\n> \n> In that case, should I set `pci->max_link_speed = 4` in the driver during\n> probe? I want to make sure this is the correct way to handle it.\n> \n\nYes\n\nBest regards,\nKrzysztof","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=iScPrbKl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52126-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"iScPrbKl\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frDFt5LLPz1xtJ\n\tfor ; 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