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{ "id": 2229593, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2229593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260428135053.251200-1-dblanzeanu@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428135053.251200-1-dblanzeanu@linux.microsoft.com>", "date": "2026-04-28T13:50:47", "name": "[0/6] target/i386/mshv: use hv_vp_register_page for fast register access", "submitter": { "id": 93106, "url": "http://patchwork.ozlabs.org/api/1.1/people/93106/?format=api", "name": "Doru Blânzeanu", "email": "dblanzeanu@linux.microsoft.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260428135053.251200-1-dblanzeanu@linux.microsoft.com/mbox/", "series": [ { "id": 501862, "url": "http://patchwork.ozlabs.org/api/1.1/series/501862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501862", "date": "2026-04-28T13:50:49", "name": "target/i386/mshv: use hv_vp_register_page for fast register access", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501862/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2229593/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=UQ0mwcmq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4htn0jpxz1yJT\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 00:01:35 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHizg-0003yi-Jf; Tue, 28 Apr 2026 10:00:56 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dblanzeanu@linux.microsoft.com>)\n id 1wHiq9-0002Ss-1W\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:05 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <dblanzeanu@linux.microsoft.com>) id 1wHiq7-0005ja-Ge\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:04 -0400", "from laptop.localdomain (unknown [86.121.140.248])\n by linux.microsoft.com (Postfix) with ESMTPSA id C446D20B716C;\n Tue, 28 Apr 2026 06:50:59 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com C446D20B716C", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1777384261;\n bh=lWFKO/4N7bNP6xaYO1XrGPYlQpmwKgGrR6emuANYzJY=;\n h=From:To:Cc:Subject:Date:From;\n b=UQ0mwcmqh2UH6w0bzqEUS8Ss/aVKCexD0YiW0QnlJEaYVoz3q3bVYpD269872Y8gk\n o5nbFnopOwRI0p5sotKEWjlz9jzPpDInIPFN1rcLYIZtVgjhuxHzntolLFIVNh+8rq\n NUNtS5OApBrrrjlgUUUIkmj/jH9mf154bMeIvHg4=", "From": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>", "Subject": "[PATCH 0/6] target/i386/mshv: use hv_vp_register_page for fast\n register access", "Date": "Tue, 28 Apr 2026 16:50:47 +0300", "Message-ID": "<20260428135053.251200-1-dblanzeanu@linux.microsoft.com>", "X-Mailer": "git-send-email 2.53.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-26", "X-Spam_score": "-2.7", "X-Spam_bar": "--", "X-Spam_report": "(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Tue, 28 Apr 2026 10:00:19 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series adds support for using the hypervisor's vp register page\nin the mshv accelerator to optimize vcpu register access on mmio and pio\nexits.\n\nCurrently, all register reads and write go through hypercalls (ioctls),\nwhich adds overhead on every VM exit. The VP register page is a shared\nmemory page that the hypervisor populates with vcpu register state,\nallowing Qemu to read and write registers directly without hypercalls.\n\nThe series is structured as follows:\n1. Remove the duplicate `fetch_guest_state` function, consolidating\n register loading into `mshv_load_regs`.\n2. Move `mshv_arch_init_vcpu` after vcpu creation so the vcpu fd is\n valid when we need it for mmap.\n3. Define the `hv_vp_register_page` structure in `hvgdk_mini.h`, matching\n the layout used by the Linux kernel's mshv driver.\n4. Set up the register page by mmapping the vcpu fd at init time. If the\n mmap fails, we fall back gracefully to the existing hypercall path.\n5. Use the register page to read registers on VM exit. General purpose\n registers, RIP, RFLAGS, segment registers, and control registers\n (CR0, CR4, CR4, CR8, EFER) are read directly from the page. Registers\n not present on the page (TR, LDTR, GDTR, IDTR, CR2, APIC_BASE) are still\n fetched via hypercall.\n6. Use register page to write registers on vmentry. GP registers,\n RIP, and RFLAGS are written to the page with the appropriate dirty\n bits set, avoiding the hypercall for the standard register store.\n\nThe register page is only used when it has been successfully mmapped and\nthe hypervisor has marked it as valid (`isvalid != 0`). Otherwise, the\nexisting hypercall-based path is used as a fallback.\n\nDoru Blânzeanu (6):\n target/i386/mshv: remove duplicate function for reading vcpu registers\n accel/mshv: move vcpu arch specific initialization after vcpu creation\n include/hw/hyperv: add hv_vp_register_page struct definition\n target/i386/mshv: hv_vp_register_page setup for the vcpu\n target/i386/mshv: use the register page to get registers\n target/i386/mshv: use the register page to set registers\n\n accel/mshv/mshv-all.c | 3 +-\n include/hw/hyperv/hvgdk_mini.h | 103 +++++++++++++++\n target/i386/cpu.h | 3 +\n target/i386/mshv/mshv-cpu.c | 221 ++++++++++++++++++++++++++++-----\n 4 files changed, 296 insertions(+), 34 deletions(-)" }