[{"id":3683652,"web_url":"http://patchwork.ozlabs.org/comment/3683652/","msgid":"<11BFD4DB-D60C-4FF8-817A-2EFADBD729B4@unpredictable.fr>","list_archive_url":null,"date":"2026-04-28T18:36:38","subject":"Re: [PATCH 0/6] target/i386/mshv: use hv_vp_register_page for fast\n register access","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 28. Apr 2026, at 15:50, Doru Blânzeanu wrote:\n> \n> This series adds support for using the hypervisor's vp register page\n> in the mshv accelerator to optimize vcpu register access on mmio and pio\n> exits.\n> \n> Currently, all register reads and write go through hypercalls (ioctls),\n> which adds overhead on every VM exit. The VP register page is a shared\n> memory page that the hypervisor populates with vcpu register state,\n> allowing Qemu to read and write registers directly without hypercalls.\n> \n> The series is structured as follows:\n> 1. Remove the duplicate `fetch_guest_state` function, consolidating\n> register loading into `mshv_load_regs`.\n> 2. Move `mshv_arch_init_vcpu` after vcpu creation so the vcpu fd is\n> valid when we need it for mmap.\n> 3. Define the `hv_vp_register_page` structure in `hvgdk_mini.h`, matching\n> the layout used by the Linux kernel's mshv driver.\n> 4. Set up the register page by mmapping the vcpu fd at init time. If the\n> mmap fails, we fall back gracefully to the existing hypercall path.\n> 5. Use the register page to read registers on VM exit. General purpose\n> registers, RIP, RFLAGS, segment registers, and control registers\n> (CR0, CR4, CR4, CR8, EFER) are read directly from the page. Registers\n> not present on the page (TR, LDTR, GDTR, IDTR, CR2, APIC_BASE) are still\n> fetched via hypercall.\n> 6. Use register page to write registers on vmentry. GP registers,\n> RIP, and RFLAGS are written to the page with the appropriate dirty\n> bits set, avoiding the hypercall for the standard register store.\n> \n> The register page is only used when it has been successfully mmapped and\n> the hypervisor has marked it as valid (`isvalid != 0`). Otherwise, the\n> existing hypercall-based path is used as a fallback.\n\nHello,\n\nSome overall comments after reading this series:\n\n- bifurcated state sync is inevitable with not syncing the full\nstate for most MMIO/I/O port accesses. \n\nIt’s wanted to skip some state. LDTR/GDTR are among the painful\nones and you’ll very much want to avoid syncing those if you can.\n\nIn the typical WHP emulation case, there’s 0 state used outside\nof the shared register page and getting there made things so much\nsmoother than otherwise.\n\n- but there’s an exception:\n\nA pattern that causes problems:\n\n /* Advance RIP and update RAX */\n rip = info->header.rip + insn_len;\n rax = info->rax;\n\n reg_names[0] = HV_X64_REGISTER_RIP;\n reg_values[0] = rip;\n reg_names[1] = HV_X64_REGISTER_RAX;\n reg_values[1] = rax;\n\n ret = set_x64_registers(cpu, reg_names, reg_values);\n if (ret < 0) {\n error_report(\"Failed to set x64 registers\");\n return -1;\n }\n\n cpu->accel->dirty = false;\n\nWhen put together with hw/i386/vmport.c, which calls cpu_synchronize_state\non an I/O port read (thankfully not very frequent), you’ll get issues with\nthis as vmport does both read and set register values on its own.\n\nIn WHPX, was dealt with in: https://patchew.org/QEMU/20260422214225.2242-1-mohamed@unpredictable.fr/20260422214225.2242-12-mohamed@unpredictable.fr/ \nand you’ll probably want to do something similar.\n\nI imagine that “cpu->accel->dirty = false;” was probably an attempt to\nget things to boot when faced with that.\n\nThis adds a small constraint that if additional state will be fetched in\nthe future, then writes have to happen either before that fetch, or on the\nnow synced state instead of the partial view.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=aIS1pGLe;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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