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{ "id": 2221144, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2221144/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260407222208.271838-1-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407222208.271838-1-pierrick.bouvier@linaro.org>", "date": "2026-04-07T22:21:47", "name": "[v11,00/21] target/arm: single-binary", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/1.1/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260407222208.271838-1-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 499177, "url": "http://patchwork.ozlabs.org/api/1.1/series/499177/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499177", "date": "2026-04-07T22:21:55", "name": "target/arm: single-binary", "version": 11, "mbox": "http://patchwork.ozlabs.org/series/499177/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2221144/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=q/6RRjID;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::629;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x629.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series tackles (most of) the rest of target/arm, especially tcg folder.\n\nWe extract tcg memory operation in a new header, with a new type representing\nvirtual addresses.\n\nInitially, I went down the way to have a dynamic definition of TCGv, which\nrequired much more boilerplate and runtime checks. After discussing with\nRichard, I realized it was not needed, and that could simply split 32 and 64 bit\nproperly in different files instead. This approach will not work with other\narchitectures, requiring something else, but it's enough for target/arm.\n\nFiles left are:\n- target/arm/tcg/mve_helper.c\n- target/arm/tcg/m_helper.c\n- target/arm/tcg/cpu32.c\n\nv11\n---\n\n- update comments\n\nv10\n---\n\n- extract patch for endianness handling in arm_disas_set_info\n- added some comments\n\nv9\n--\n\n- introduce aarch64_translate_code *before* adding parameter to translator_loop\n- use TCG_TYPE_VA as address type for translator_loop\n- remove inline marker on functions merged from arm_ldst.h to translate.c\n- refactor arm_ldl_code/arm_lduw_code\n\nv8\n--\n\n- make translate.c compilation unit common.\n\nv7\n--\n\n- add parameter to translator_loop to indicate address type for current tb.\n- remove TCGv from target/arm/tcg/translate.c\n\nv6\n--\n\n- meson.build: extract decode files in separate variables and explicitly include\n them in user and system code. The duplication is now minimized: one instance\n for all system binaries, and one per user binary.\n\nv5\n--\n\n- reimplemented what v0 did with new approach defining new tcg-op-mem header\n- reapply all straightforward patches from v0\n- only translate.c is left, but first want to validate that changes here are ok\n for maintainers before doing more.\n\nv0\n--\n\nSee original thread:\nhttps://lore.kernel.org/qemu-devel/20260109053158.2800705-1-pierrick.bouvier@linaro.org/#t\n\nNote about v1 -> v4\n-------------------\n\n- After v0 which was trying to do too many changes, v1 to v4 focused on smaller\n things, and all patches have been merged already.\n https://patchew.org/QEMU/20260219040150.2098396-1-pierrick.bouvier@linaro.org/\n\nPierrick Bouvier (21):\n include/tcg/tcg-op: extract memory operations to tcg-op-mem.h\n target/arm/translate.h: remove tcg-op.h include\n target/arm/tcg/translate.h: remove tcg-op-gvec.h include\n target/arm/tcg/translate.h: remove TARGET_AARCH64\n target/arm/tcg/translate-vfp.c: make compilation unit common\n target/arm/tcg/translate-neon.c: make compilation unit common\n target/arm/tcg/translate-mve.c: make compilation unit common\n target/arm/tcg/translate-m-nocp.c: make compilation unit common\n target/arm/tcg/op_helper.c: make compilation unit common\n target/arm/tcg/gengvec.c: make compilation unit common\n target/arm/tcg/translate.c: remove MO_TE usage\n target/arm/tcg/translate.c: replace target_ulong with uint32_t\n target/arm/tcg/translate.c: extract aarch64_translate_code()\n tcg/translator: add parameter to translator_loop for current addr type\n target/arm/tcg/translate.c: replace TCGv with TCGv_va\n target/arm/tcg/translate-a64.c: use translator_ldl_end instead of\n arm_ldl_code\n target/arm/tcg/arm_ldst.h: merge in translate.c\n target/arm/tcg/translate.c: replace translator_ldl_swap with\n translator_ldl_end\n target/arm/cpu.c: simplify endianness handling in arm_disas_set_info\n target/arm/tcg/translate.c: remove target_ulong\n target/arm/tcg/translate.c: make compilation unit common\n\n include/exec/translator.h | 4 +-\n include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++\n include/tcg/tcg-op.h | 100 +-----------------------\n target/arm/internals.h | 2 +\n target/arm/tcg/arm_ldst.h | 47 ------------\n target/arm/tcg/translate.h | 14 +---\n accel/tcg/translate-all.c | 1 -\n accel/tcg/translator.c | 4 +-\n target/alpha/translate.c | 3 +-\n target/arm/cpu.c | 6 +-\n target/arm/tcg/op_helper.c | 1 -\n target/arm/tcg/stubs32.c | 24 ++++++\n target/arm/tcg/translate-a64.c | 17 ++++-\n target/arm/tcg/translate-sme.c | 1 +\n target/arm/tcg/translate-sve.c | 1 +\n target/arm/tcg/translate.c | 73 +++++++++++-------\n target/avr/translate.c | 3 +-\n target/hexagon/translate.c | 3 +-\n target/hppa/translate.c | 3 +-\n target/i386/tcg/translate.c | 3 +-\n target/loongarch/tcg/translate.c | 3 +-\n target/m68k/translate.c | 3 +-\n target/microblaze/translate.c | 3 +-\n target/mips/tcg/translate.c | 3 +-\n target/or1k/translate.c | 3 +-\n target/ppc/translate.c | 3 +-\n target/riscv/translate.c | 3 +-\n target/rx/translate.c | 3 +-\n target/s390x/tcg/translate.c | 3 +-\n target/sh4/translate.c | 3 +-\n target/sparc/translate.c | 3 +-\n target/tricore/translate.c | 3 +-\n target/xtensa/translate.c | 3 +-\n target/arm/tcg/meson.build | 57 ++++++++++----\n 34 files changed, 304 insertions(+), 228 deletions(-)\n create mode 100644 include/tcg/tcg-op-mem.h\n create mode 100644 target/arm/tcg/stubs32.c" }