diff mbox

[U-Boot,v2,10/12] jetson-tk1: Add PSCI configuration options and reserve secure code

Message ID c5b6ceeb69c0cfd13d7bb470ab667fe42de1e0cd.1424091289.git.jan.kiszka@siemens.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Jan Kiszka Feb. 16, 2015, 12:54 p.m. UTC 
From: Ian Campbell <ijc@hellion.org.uk>

The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 arch/arm/cpu/armv7/tegra124/Kconfig | 2 ++
 include/configs/jetson-tk1.h        | 5 +++++
 2 files changed, 7 insertions(+)

Comments

Stephen Warren Feb. 17, 2015, 9:05 p.m. UTC | #1 
On 02/16/2015 05:54 AM, Jan Kiszka wrote:
> The secure world code is relocated to the MB just below the top of 4G, we
> reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
> not protected in h/w. See next patch.

> diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h

> +#define CONFIG_ARMV7_PSCI			1
> +/* Reserve top 1M for secure RAM */
> +#define CONFIG_ARMV7_SECURE_BASE		0xfff00000

Can that not be dynamic? What if the system only has 1GB RAM not 2GB. 
It's true that all shipped/public versions of this board do have 2GB 
AFAIK, but we have had internal versions with different amounts of RAM, 
and I don't think there's anything else in Tegra U-Boots that hard-codes 
RAM sizes.

> +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
Jan Kiszka Feb. 18, 2015, 7:39 a.m. UTC | #2 
On 2015-02-17 22:05, Stephen Warren wrote:
> On 02/16/2015 05:54 AM, Jan Kiszka wrote:
>> The secure world code is relocated to the MB just below the top of 4G, we
>> reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE)
>> but it is
>> not protected in h/w. See next patch.
> 
>> diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
> 
>> +#define CONFIG_ARMV7_PSCI            1
>> +/* Reserve top 1M for secure RAM */
>> +#define CONFIG_ARMV7_SECURE_BASE        0xfff00000
> 
> Can that not be dynamic? What if the system only has 1GB RAM not 2GB.
> It's true that all shipped/public versions of this board do have 2GB
> AFAIK, but we have had internal versions with different amounts of RAM,
> and I don't think there's anything else in Tegra U-Boots that hard-codes
> RAM sizes.

I tested and checked the PSCI code again, and it turned out to be not
position independent yet (vector tables, functions pointers). Everything
can be fixed, but I wonder if this shouldn't be done on top, when we
have a concrete need.

Locating the monitor may involve more factors on different SoCs and
boards. So a general solution may be more complicated, even when dynamic
relocation itself is solved.

Jan
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig
index 88f627c..5114299 100644
--- a/arch/arm/cpu/armv7/tegra124/Kconfig
+++ b/arch/arm/cpu/armv7/tegra124/Kconfig
@@ -5,6 +5,8 @@  choice
 
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
+	select CPU_V7_HAS_NONSEC if !SPL_BUILD
+	select CPU_V7_HAS_VIRT if !SPL_BUILD
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chrombook"
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 0a79c7c..80c2952 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -81,4 +81,9 @@ 
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
+#define CONFIG_ARMV7_PSCI			1
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
 #endif /* __CONFIG_H */