diff mbox series

[v2,2/2] riscv: Enable cpu clock if it is present

Message ID 56bbd0a4-5ec0-7af1-eed5-c93e2a81b677@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series [v2,1/2] riscv: Try to get cpu frequency from device tree | expand

Commit Message

Sean Anderson Feb. 2, 2020, 5:39 p.m. UTC
The cpu clock is probably already enabled if we are executing code
(though we could be executing from a different core). This patch
prevents the cpu clock or its parents from being disabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
  This doesn't strictly depend on the previous patch, but it doesn't
  make too much sense without it.

  Changes for v2:
    - New
 drivers/cpu/riscv_cpu.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Bin Meng Feb. 4, 2020, 10:36 a.m. UTC | #1
On Mon, Feb 3, 2020 at 1:40 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> The cpu clock is probably already enabled if we are executing code
> (though we could be executing from a different core). This patch
> prevents the cpu clock or its parents from being disabled.
>
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> ---
>   This doesn't strictly depend on the previous patch, but it doesn't
>   make too much sense without it.
>
>   Changes for v2:
>     - New
>  drivers/cpu/riscv_cpu.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

I believe both 2 patches in this series are needed by "riscv: Add
Sipeed Maix support" series?
If yes, I think you can just put 2 patches into the same series, to
give people a good context next time.

Regards,
Bin
diff mbox series

Patch

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5309a49e60..52b74d9e69 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -1,6 +1,7 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  */
 
 #include <clk.h>
@@ -116,6 +117,24 @@  static int riscv_cpu_bind(struct udevice *dev)
 	return 0;
 }
 
+static int riscv_cpu_probe(struct udevice *dev)
+{
+	int ret = 0;
+	struct clk clk;
+
+	/* Get a clock if it exists */
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return 0;
+
+	ret = clk_enable(&clk);
+	clk_free(&clk);
+	if (ret == -ENOSYS || ret == -ENOTSUPP)
+		return 0;
+	else
+		return ret;
+}
+
 static const struct cpu_ops riscv_cpu_ops = {
 	.get_desc	= riscv_cpu_get_desc,
 	.get_info	= riscv_cpu_get_info,
@@ -132,6 +151,7 @@  U_BOOT_DRIVER(riscv_cpu) = {
 	.id = UCLASS_CPU,
 	.of_match = riscv_cpu_ids,
 	.bind = riscv_cpu_bind,
+	.probe = riscv_cpu_probe,
 	.ops = &riscv_cpu_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };