From 43e2aa1dd77221e10479a4352a50332942beeb38 Mon Sep 17 00:00:00 2001
From: Mauro Condarelli <mc5686@mclink.it>
Date: Sat, 4 Jan 2020 00:31:54 +0100
Subject: [PATCH] Port to VoCore2 board.
Signed-off-by: Mauro Condarelli <mc5686@mclink.it>
---
arch/mips/dts/Makefile | 1 +
arch/mips/dts/mt7628a.dtsi | 18 +++++-
arch/mips/dts/vocore_vocore2.dts | 83 ++++++++++++++++++++++++++++
arch/mips/mach-mtmips/Kconfig | 9 +++
board/vocore/vocore2/Kconfig | 11 ++++
board/vocore/vocore2/Makefile | 2 +
board/vocore/vocore2/board.c | 35 ++++++++++++
configs/vocore_vocore2_defconfig | 70 +++++++++++++++++++++++
drivers/clk/Kconfig | 8 +++
drivers/clk/Makefile | 1 +
drivers/clk/clk-mtmips-cg.c | 63 +++++++++++++++++++++
drivers/phy/Kconfig | 2 +
include/configs/vocore2.h | 43 ++++++++++++++
include/dt-bindings/clk/mt7628-clk.h | 31 +++++++++++
14 files changed, 376 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/vocore_vocore2.dts
create mode 100644 board/vocore/vocore2/Kconfig
create mode 100644 board/vocore/vocore2/Makefile
create mode 100644 board/vocore/vocore2/board.c
create mode 100644 configs/vocore_vocore2_defconfig
create mode 100644 drivers/clk/clk-mtmips-cg.c
create mode 100644 include/configs/vocore2.h
create mode 100644 include/dt-bindings/clk/mt7628-clk.h
@@ -22,6 +22,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
+dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
@@ -61,6 +61,12 @@
u-boot,dm-pre-reloc;
};
+ clkgate: clkgate@0x30 {
+ reg = <0x30 0x4>;
+ compatible = "mediatek,mtmips-clk-gate";
+ #clock-cells = <1>;
+ };
+
rstctrl: rstctrl@0x34 {
reg = <0x34 0x4>;
compatible = "mediatek,mtmips-reset";
@@ -397,9 +403,19 @@
builtin-cd = <1>;
r_smpl = <1>;
- clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+
+ clocks = <&clk48m>, <&clk48m>;
clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sd_iot_mode>;
+ pinctrl-1 = <&sd_iot_mode>;
+
+ vmmc-supply = <&clk48m>;
+ vqmmc-supply = <&clk48m>;
+
resets = <&rstctrl MT7628_SDXC_RST>;
status = "disabled";
new file mode 100644
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ */
+
+/dts-v1/;
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+ model = "VoCore2";
+
+ aliases {
+ serial0 = &uart2;
+ spi0 = &spi0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200 root=/dev/mtdblock4 rootfstype=squashfs USE=SD";
+ stdout-path = &uart2;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ p0led {
+ groups = "p0led_a";
+ function = "led";
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ nor0: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ spi-max-frequency = <10000000>;
+ reg = <0x0>;
+ m25p,chunked-io = <32>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x50000>;
+ };
+ partition@50000 {
+ label = "kernel";
+ reg = <0x50000 0x2b0000>;
+ };
+ partition@300000 {
+ label = "filesystem";
+ reg = <0x300000 0xcfe000>;
+ };
+ partition@ffe000 {
+ label = "env";
+ reg = <0xffe000 0x001000>;
+ };
+ eeprom: partition@fff000 {
+ label = "factory";
+ reg = <0xfff000 0x001000>;
+ };
+ };
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ephy_iot_mode>;
+ mediatek,poll-link-phy = <0>;
+};
+
+&mmc {
+ status = "okay";
+};
@@ -43,6 +43,14 @@ config BOARD_LINKIT_SMART_7688
ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
a MT7688 (PCIe).
+config BOARD_VOCORE2
+ bool "VoCore2"
+ depends on SOC_MT7628
+ select SUPPORTS_BOOT_RAM
+ help
+ VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM
+ and 16 MiB of flash (SPI).
+
endchoice
choice
@@ -134,5 +142,6 @@ config SUPPORTS_BOOT_RAM
source "board/gardena/smart-gateway-mt7688/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
+source "board/vocore/vocore2/Kconfig"
endmenu
new file mode 100644
@@ -0,0 +1,11 @@
+if BOARD_VOCORE2
+config SYS_BOARD
+ default "vocore2"
+
+config SYS_VENDOR
+ default "vocore"
+
+config SYS_CONFIG_NAME
+ default "vocore2"
+
+endif
new file mode 100644
@@ -0,0 +1,2 @@
+
+obj-y := board.o
new file mode 100644
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Mauro Condarelli <mc5686@mclink.it>
+ *
+ * Note: this is largely copied from:
+ * board/seeed/linkit_smart_7688/board.c
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MT76XX_GPIO1_MODE 0x10000060
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+ void __iomem *gpio_mode;
+
+ /* Select UART2 mode instead of GPIO mode (default) */
+ gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
+ clrbits_le32(gpio_mode, GENMASK(27, 26));
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * The pin muxing of UART2 also needs to be done, if debug uart
+ * is not enabled. So we need to call this function here as well.
+ */
+ board_debug_uart_init();
+
+ return 0;
+}
new file mode 100644
@@ -0,0 +1,70 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000
+CONFIG_ENV_SIZE=0x00001000
+CONFIG_ENV_OFFSET=0x00FFE000
+CONFIG_ENV_SECT_SIZE=0x00001000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_BOARD_VOCORE2=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BOOT_GET_KBD=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_LOGLEVEL=8
+CONFIG_VERSION_VARIABLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_AUTOBOOT is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="spi0.0:320k(u-boot),2752k(kernel),13304k(filesystem),4k(env),-(factory)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_ADDR=0x00FFE000
+# CONFIG_NET is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_BLK=y
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MTD=y
+# CONFIG_DM_ETH is not set
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=3
+CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
+CONFIG_SYSRESET_SYSCON=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
@@ -176,4 +176,12 @@ config SANDBOX_CLK_CCF
Enable this option if you want to test the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
+config CLK_MTMIPS_GATE
+ bool "Enable clock gating driver for MediaTek MIPS platform"
+ depends on CLK && ARCH_MTMIPS
+ default y
+ help
+ Enable clock gating driver for MediaTek MIPS platform.
+ This driver supports only clock enable and disable.
+
endmenu
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
+obj-$(CONFIG_CLK_MTMIPS_GATE) += clk-mtmips-cg.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
new file mode 100644
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/io.h>
+
+struct mtmips_clk_gate_priv {
+ void __iomem *base;
+};
+
+static int mtmips_clk_gate_enable(struct clk *clk)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev);
+
+ setbits_32(priv->base, BIT(clk->id));
+
+ return 0;
+}
+
+static int mtmips_clk_gate_disable(struct clk *clk)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(clk->dev);
+
+ clrbits_32(priv->base, BIT(clk->id));
+
+ return 0;
+}
+
+const struct clk_ops mtmips_clk_gate_ops = {
+ .enable = mtmips_clk_gate_enable,
+ .disable = mtmips_clk_gate_disable,
+};
+
+static int mtmips_clk_gate_probe(struct udevice *dev)
+{
+ struct mtmips_clk_gate_priv *priv = dev_get_priv(dev);
+
+ priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
+ if (!priv->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id mtmips_clk_gate_ids[] = {
+ { .compatible = "mediatek,mtmips-clk-gate" },
+ { }
+};
+
+U_BOOT_DRIVER(mtmips_clk_gate) = {
+ .name = "mtmips-clk-gate",
+ .id = UCLASS_CLK,
+ .of_match = mtmips_clk_gate_ids,
+ .probe = mtmips_clk_gate_probe,
+ .priv_auto_alloc_size = sizeof(struct mtmips_clk_gate_priv),
+ .ops = &mtmips_clk_gate_ops,
+};
@@ -201,6 +201,8 @@ config MT76X8_USB_PHY
bool "MediaTek MT76x8 (7628/88) USB PHY support"
depends on PHY
depends on SOC_MT7628
+ select CLK
+ select DM_RESET
help
Support the USB PHY in MT76x8 SoCs
new file mode 100644
@@ -0,0 +1,43 @@
+#ifndef __VOCORE2_CONFIG_H__
+#define __VOCORE2_CONFIG_H__
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#ifdef CONFIG_BOOT_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 921600 }
+#define CONFIG_BAUDRATE 115200
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#endif
+
+#endif//__VOCORE2_CONFIG_H__
new file mode 100644
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7628_CLK_H_
+#define _DT_BINDINGS_MT7628_CLK_H_
+
+#define MT7628_PWM_CLK 31
+#define MT7628_SDXC_CLK 30
+#define MT7628_CRYPTO_CLK 29
+#define MT7628_MIPS_CNT_CLK 28
+#define MT7628_PCIE_CLK 26
+#define MT7628_UPHY_CLK 25
+#define MT7628_ETH_CLK 23
+#define MT7628_UART2_CLK 20
+#define MT7628_UART1_CLK 19
+#define MT7628_SPI_CLK 18
+#define MT7628_I2S_CLK 17
+#define MT7628_I2C_CLK 16
+#define MT7628_GDMA_CLK 14
+#define MT7628_PIO_CLK 13
+#define MT7628_UART0_CLK 12
+#define MT7628_PCM_CLK 11
+#define MT7628_MC_CLK 10
+#define MT7628_INT_CLK 9
+#define MT7628_TIMER_CLK 8
+
+#endif /* _DT_BINDINGS_MT7628_CLK_H_ */
--
2.25.0.rc0