| Message ID | 20240516090031.2373-5-anand@edgeble.ai |
|---|---|
| State | New |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [v1,1/9] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC | expand |
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ba1474bb9e..1fd482e43b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -297,6 +297,7 @@ config ROCKCHIP_RK3399 imply TPL_SYS_MALLOC_SIMPLE imply TPL_SYSCON imply TPL_TINY_MEMSET + imply DISPLAY_CPUINFO help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index acfe393410..2c1a8141c0 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -30,7 +30,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 95fdb418d8..f6649804c7 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -31,7 +31,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y
Imply DISPLAY_CPUINFO Kconfig options to support on all RK3399 boards, Its used to determine the reset cause of the board. Cc: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Anand Moon <anand@edgeble.ai> --- arch/arm/mach-rockchip/Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/chromebook_kevin_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-)