| Message ID | 20240407202118.51854-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | 3242dd0ac91ea4fd9cf516f0d196a34ea23367de |
| Delegated to: | Patrice Chotard |
| Headers | show |
| Series | [v2] ARM: stm32: Jump to ep on successful resume in PSCI suspend code | expand |
On 4/7/24 22:21, Marek Vasut wrote: > In case the system has resumed successfully, the PSCI suspend resume > code has to jump to the 'ep' successful resume entry point code path, > otherwise the code has to jump to content of the LR register, which > points to failed resume code path. > > To implement this distinction, rewrite LR register stored on stack > with 'ep' value in case of a successful resume, which is really in > every case unless some catastrophic failure occurred during suspend. > > Without this change, Linux counts every resume as failed in > /sys/power/suspend_stats/fail > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Patrice Chotard <patrice.chotard@foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> > Cc: u-boot@dh-electronics.com > Cc: u-boot@lists.denx.de > Cc: uboot-stm32@st-md-mailman.stormreply.com > --- > V2: Rebase on u-boot/master > --- > arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c > index 8cdeb0ab3f2..4f2379df45f 100644 > --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c > +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c > @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > { > u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; > u32 gicd_addr = stm32mp_get_gicd_base_address(); > + u32 cpu = psci_get_cpu_id(); > + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); > bool iwdg1_wake = false; > bool iwdg2_wake = false; > bool other_wake = false; > @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > > writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); > clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); > + > + /* > + * The system has resumed successfully. Rewrite LR register stored > + * on stack with 'ep' value, so that on return from this PSCI call, > + * the code would jump to that 'ep' resume entry point code path > + * instead of the previous 'lr' register content which (e.g. with > + * Linux) points to resume failure code path. > + * > + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout > + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. > + */ > + writel(ep, sp - 8); > } Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Thanks Patrice
On 4/7/24 22:21, Marek Vasut wrote: > In case the system has resumed successfully, the PSCI suspend resume > code has to jump to the 'ep' successful resume entry point code path, > otherwise the code has to jump to content of the LR register, which > points to failed resume code path. > > To implement this distinction, rewrite LR register stored on stack > with 'ep' value in case of a successful resume, which is really in > every case unless some catastrophic failure occurred during suspend. > > Without this change, Linux counts every resume as failed in > /sys/power/suspend_stats/fail > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Patrice Chotard <patrice.chotard@foss.st.com> > Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> > Cc: u-boot@dh-electronics.com > Cc: u-boot@lists.denx.de > Cc: uboot-stm32@st-md-mailman.stormreply.com > --- > V2: Rebase on u-boot/master > --- > arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c > index 8cdeb0ab3f2..4f2379df45f 100644 > --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c > +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c > @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > { > u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; > u32 gicd_addr = stm32mp_get_gicd_base_address(); > + u32 cpu = psci_get_cpu_id(); > + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); > bool iwdg1_wake = false; > bool iwdg2_wake = false; > bool other_wake = false; > @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > > writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); > clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); > + > + /* > + * The system has resumed successfully. Rewrite LR register stored > + * on stack with 'ep' value, so that on return from this PSCI call, > + * the code would jump to that 'ep' resume entry point code path > + * instead of the previous 'lr' register content which (e.g. with > + * Linux) points to resume failure code path. > + * > + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout > + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. > + */ > + writel(ep, sp - 8); > } Applied on u-boot-stm32/master
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); }
In case the system has resumed successfully, the PSCI suspend resume code has to jump to the 'ep' successful resume entry point code path, otherwise the code has to jump to content of the LR register, which points to failed resume code path. To implement this distinction, rewrite LR register stored on stack with 'ep' value in case of a successful resume, which is really in every case unless some catastrophic failure occurred during suspend. Without this change, Linux counts every resume as failed in /sys/power/suspend_stats/fail Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- V2: Rebase on u-boot/master --- arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)