diff mbox series

[v2,2/3] riscv: dts: sophgo: Add clk node and sdhci node

Message ID 20240309175330.79267-3-seashell11234455@gmail.com
State Accepted
Commit b0a09b21e913804451b2abb059a85c99189e8002
Delegated to: Andes
Headers show
Series mmc: sophgo: milkv_duo: Add SD card support for Milk-V Duo board | expand

Commit Message

Kongyang Liu March 9, 2024, 5:51 p.m. UTC
Add clk node and sdhci node for cv18xx SoCs according to patches from Linux
kernel.

clk: https://lore.kernel.org/all/IA1PR20MB4953F9AD6792013B54636F05BB4F2@IA1PR20MB4953.namprd20.prod.outlook.com/
sdhci: https://lore.kernel.org/all/20240217144826.3944-1-jszhang@kernel.org/

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>

---

Changes in v2:
- Sync device tree with ptaches from Linux kernel

 arch/riscv/dts/cv1800b-milkv-duo.dts |  8 ++++++++
 arch/riscv/dts/cv1800b.dtsi          |  4 ++++
 arch/riscv/dts/cv18xx.dtsi           | 22 ++++++++++++++++++++++
 3 files changed, 34 insertions(+)

Comments

Leo Liang March 12, 2024, 9:27 a.m. UTC | #1
On Sun, Mar 10, 2024 at 01:51:56AM +0800, Kongyang Liu wrote:
> Add clk node and sdhci node for cv18xx SoCs according to patches from Linux
> kernel.
> 
> clk: https://lore.kernel.org/all/IA1PR20MB4953F9AD6792013B54636F05BB4F2@IA1PR20MB4953.namprd20.prod.outlook.com/
> sdhci: https://lore.kernel.org/all/20240217144826.3944-1-jszhang@kernel.org/
> 
> Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
> ---
> 
> Changes in v2:
> - Sync device tree with ptaches from Linux kernel
> 
>  arch/riscv/dts/cv1800b-milkv-duo.dts |  8 ++++++++
>  arch/riscv/dts/cv1800b.dtsi          |  4 ++++
>  arch/riscv/dts/cv18xx.dtsi           | 22 ++++++++++++++++++++++
>  3 files changed, 34 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 3af9e34b3b..94e64ddce8 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -33,6 +33,14 @@ 
 	clock-frequency = <25000000>;
 };
 
+&sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	no-mmc;
+	no-sdio;
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e320a..baf641829e 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@ 
 &clint {
 	compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
 };
+
+&clk {
+	compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4b1e..ec99c4deeb 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -45,6 +45,13 @@ 
 		#clock-cells = <0>;
 	};
 
+	sdhci_clk: sdhci-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <375000000>;
+		clock-output-names = "sdhci_clk";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -53,6 +60,12 @@ 
 		dma-noncoherent;
 		ranges;
 
+		clk: clock-controller@3002000 {
+			reg = <0x03002000 0x1000>;
+			clocks = <&osc>;
+			#clock-cells = <1>;
+		};
+
 		gpio0: gpio@3020000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x3020000 0x1000>;
@@ -175,6 +188,15 @@ 
 			status = "disabled";
 		};
 
+		sdhci0: mmc@4310000 {
+			compatible = "sophgo,cv1800b-dwcmshc";
+			reg = <0x4310000 0x1000>;
+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sdhci_clk>;
+			clock-names = "core";
+			status = "disabled";
+		};
+
 		plic: interrupt-controller@70000000 {
 			reg = <0x70000000 0x4000000>;
 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;