diff mbox series

[4/5] mmc: zynq_sdhci: disable OTAPDLYENA

Message ID 20240223140613.1240570-4-lists@steffen.cc
State New
Delegated to: Michal Simek
Headers show
Series [1/5] configs: zynqmp: don't remove power-domains for spl device tree | expand

Commit Message

Steffen Dirkwinkel Feb. 23, 2024, 2:06 p.m. UTC 
From: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>

This ports a change from arm-trusted-firmware:
commit: fe1fa205fca4d1dd4a1b1755942956dbca65d573 in arm-trusted-firmware
(https://github.com/ARM-software/arm-trusted-firmware/commit/fe1fa205fca4d1dd4a1b1755942956dbca65d573)
The ITAPDLYENA change is in another commit.

We shouldn't have different behavior for u-boot-SPL and u-boot so let's
use the same logic here.

Message from arm-trusted-firmware:
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.

Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
---

 drivers/mmc/zynq_sdhci.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 79bb8ba66d9..06b782eb79a 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -45,6 +45,7 @@ 
 #define SD1_TAP_OFFSET			16
 #define SD0_ITAPCHGWIN			BIT(9)
 #define SD0_ITAPDLYENA			BIT(8)
+#define SD0_OTAPDLYENA			BIT(6)
 #define SD0_ITAPDLYSEL_MASK		GENMASK(7, 0)
 #define SD0_OTAPDLYSEL_MASK		GENMASK(5, 0)
 
@@ -316,6 +317,7 @@  static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
 
 static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
 {
+	int ret;
 	u32 shift;
 
 	if (node_id == NODE_SD_0)
@@ -326,6 +328,12 @@  static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
 		return -EINVAL;
 
 	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+		ret = zynqmp_mmio_write(SD_OTAP_DLY,
+					SD0_OTAPDLYENA << shift,
+					0);
+		if (ret)
+			return ret;
+
 		return zynqmp_mmio_write(SD_OTAP_DLY,
 						SD0_OTAPDLYSEL_MASK << shift,
 						otap_delay << shift);