| Message ID | 20240202093748.330658-2-seashell11234455@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: cpu: Add support for cv1800b SoC | expand |
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> 于2024年2月2日周五 19:11写道： > > On 02.02.24 10:37, Kongyang Liu wrote: > > Add Sophgo cv1800b SoC to support RISC-V arch. > > > > Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> > > > > --- > > > > arch/riscv/Kconfig | 1 + > > arch/riscv/cpu/cv1800b/Kconfig | 12 ++++++++++++ > > arch/riscv/cpu/cv1800b/Makefile | 6 ++++++ > > arch/riscv/cpu/cv1800b/cpu.c | 22 ++++++++++++++++++++++ > > arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++++++++ > > board/sophgo/milkv_duo/Kconfig | 4 ++-- > > 6 files changed, 64 insertions(+), 2 deletions(-) > > create mode 100644 arch/riscv/cpu/cv1800b/Kconfig > > create mode 100644 arch/riscv/cpu/cv1800b/Makefile > > create mode 100644 arch/riscv/cpu/cv1800b/cpu.c > > create mode 100644 arch/riscv/cpu/cv1800b/dram.c > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index ac52c5e6da..2c92b0d9f6 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig" > > > > # platform-specific options below > > source "arch/riscv/cpu/andesv5/Kconfig" > > +source "arch/riscv/cpu/cv1800b/Kconfig" > > source "arch/riscv/cpu/fu540/Kconfig" > > source "arch/riscv/cpu/fu740/Kconfig" > > source "arch/riscv/cpu/generic/Kconfig" > > diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig > > new file mode 100644 > > index 0000000000..7225b1210c > > --- /dev/null > > +++ b/arch/riscv/cpu/cv1800b/Kconfig > > @@ -0,0 +1,12 @@ > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > > + > > +config SOPHGO_CV1800B > > + bool > > + select ARCH_EARLY_INIT_R > > + select SYS_CACHE_SHIFT_6 > > + imply CPU > > + imply CPU_RISCV > > + imply RISCV_TIMER > > + imply CMD_CPU > > diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile > > new file mode 100644 > > index 0000000000..da12e0f64e > > --- /dev/null > > +++ b/arch/riscv/cpu/cv1800b/Makefile > > @@ -0,0 +1,6 @@ > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> > > + > > +obj-y += dram.o > > +obj-y += cpu.o > > diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c > > new file mode 100644 > > index 0000000000..f13c18942f > > --- /dev/null > > +++ b/arch/riscv/cpu/cv1800b/cpu.c > > @@ -0,0 +1,22 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> > > + */ > > + > > +#include <irq_func.h> > > +#include <asm/cache.h> > > + > > +/* > > + * cleanup_before_linux() is called just before we call linux > > + * it prepares the processor for linux > > + * > > + * we disable interrupt and caches. > > + */ > > +int cleanup_before_linux(void) > > +{ > > + disable_interrupts(); > > + > > + cache_flush(); > > + > > + return 0; > > +} > > Thank you for enabling another board. > > The same cleanup_before_linux() code can be found in: > > arch/riscv/cpu/fu740/cpu.c > arch/riscv/cpu/andesv5/cpu.c > arch/riscv/cpu/fu540/cpu.c > arch/riscv/cpu/generic/cpu.c > arch/riscv/cpu/jh7110/cpu.c > > We should try to avoid this code duplication. > > disable_interrupts() is already called by bootm_disable_interrupts(). > > flushing the instruction cache after loading a binary is not > architecture specific either. This is why bootm_load_os() calls > flush_cache(). > > It should be sufficient to let weak function flush_dcache_range() in > arch/riscv/lib/cache.c call flush_dcache_all(). And then remove all > cleanup_before_linux() implementations. > Thanks for your explanation. Currently, we have only implemented cache for SoC cv1800b, and for the sake of compatibility, the remaining code has been simply copied from the generic folder without a thorough examination. If this function is unnecessary, it will be removed in the next version. Best regards Kongyang Liu > Best regards > > Heinrich > > > > diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c > > new file mode 100644 > > index 0000000000..91007c0a3d > > --- /dev/null > > +++ b/arch/riscv/cpu/cv1800b/dram.c > > @@ -0,0 +1,21 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> > > + */ > > + > > +#include <fdtdec.h> > > +#include <init.h> > > +#include <asm/global_data.h> > > +#include <linux/sizes.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +int dram_init(void) > > +{ > > + return fdtdec_setup_mem_size_base(); > > +} > > + > > +int dram_init_banksize(void) > > +{ > > + return fdtdec_setup_memory_banksize(); > > +} > > diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig > > index 2a458f291c..040a7487f1 100644 > > --- a/board/sophgo/milkv_duo/Kconfig > > +++ b/board/sophgo/milkv_duo/Kconfig > > @@ -7,7 +7,7 @@ config SYS_VENDOR > > default "sophgo" > > > > config SYS_CPU > > - default "generic" > > + default "cv1800b" > > > > config SYS_CONFIG_NAME > > default "milkv_duo" > > @@ -23,6 +23,6 @@ config ENV_SECT_SIZE > > > > config BOARD_SPECIFIC_OPTIONS > > def_bool y > > - select GENERIC_RISCV > > + select SOPHGO_CV1800B > > > > endif >
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ac52c5e6da..2c92b0d9f6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig new file mode 100644 index 0000000000..7225b1210c --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config SOPHGO_CV1800B + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply CMD_CPU diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile new file mode 100644 index 0000000000..da12e0f64e --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c new file mode 100644 index 0000000000..f13c18942f --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cpu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <irq_func.h> +#include <asm/cache.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c new file mode 100644 index 0000000000..91007c0a3d --- /dev/null +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig index 2a458f291c..040a7487f1 100644 --- a/board/sophgo/milkv_duo/Kconfig +++ b/board/sophgo/milkv_duo/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "sophgo" config SYS_CPU - default "generic" + default "cv1800b" config SYS_CONFIG_NAME default "milkv_duo" @@ -23,6 +23,6 @@ config ENV_SECT_SIZE config BOARD_SPECIFIC_OPTIONS def_bool y - select GENERIC_RISCV + select SOPHGO_CV1800B endif
Add Sophgo cv1800b SoC to support RISC-V arch. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> --- arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 ++++++++++++ arch/riscv/cpu/cv1800b/Makefile | 6 ++++++ arch/riscv/cpu/cv1800b/cpu.c | 22 ++++++++++++++++++++++ arch/riscv/cpu/cv1800b/dram.c | 21 +++++++++++++++++++++ board/sophgo/milkv_duo/Kconfig | 4 ++-- 6 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c