| Message ID | 20231214140937.27784-3-zong.li@sifive.com |
|---|---|
| State | Accepted |
| Commit | 40c76dfed29ac2173bd32d730979ef2531029048 |
| Delegated to: | Andes |
| Headers | show |
| Series | Add SiFive private L2 cache driver | expand |
On Thu, Dec 14, 2023 at 02:09:37PM +0000, Zong Li wrote: > The power gating feature of pl2 should be enabled as early as possible, > it would be better to put it in SPL stage. > > Signed-off-by: Zong Li <zong.li@sifive.com> > --- > arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index 39b0248c32..d8fe1dfa95 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -7,7 +7,10 @@ #include <cpu_func.h> #include <log.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#ifndef CONFIG_SPL_BUILD void enable_caches(void) { struct udevice *dev; @@ -25,3 +28,21 @@ void enable_caches(void) log_debug("ccache enable failed"); } } +#else +static inline void probe_cache_device(struct driver *driver, struct udevice *dev) +{ + for (uclass_find_first_device(UCLASS_CACHE, &dev); + dev; + uclass_find_next_device(&dev)) { + if (dev->driver == driver) + device_probe(dev); + } +} + +void enable_caches(void) +{ + struct udevice *dev = NULL; + + probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); +} +#endif /* !CONFIG_SPL_BUILD */
The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> --- arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)