diff mbox series

mips: fix change_k0_cca()

Message ID 20231106165241.298426-1-daniel.schwierzeck@gmail.com
State Under Review
Delegated to: Daniel Schwierzeck
Headers show
Series mips: fix change_k0_cca() | expand

Commit Message

Daniel Schwierzeck Nov. 6, 2023, 4:52 p.m. UTC
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.

Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.

Reported by user ddqxy138 on Github.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>


 arch/mips/lib/cache_init.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 602741c65d..d64209d76a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -431,9 +431,9 @@  LEAF(change_k0_cca)
 	xor		a0, a0, t0
 	andi		a0, a0, CONF_CM_CMASK
-	xor		a0, a0, t0
+	xor		t0, a0, t0
-	mtc0		a0, CP0_CONFIG
+	mtc0		t0, CP0_CONFIG
 	jr.hb		ra