diff mbox series

pci: xilinx: Enable MMIO region

Message ID 20231102082303.354944-4-mchitale@ventanamicro.com
State Superseded
Delegated to: Michal Simek
Headers show
Series pci: xilinx: Enable MMIO region | expand

Commit Message

Mayuresh Chitale Nov. 2, 2023, 8:23 a.m. UTC 
The host bridge MMIO region is disabled by default due to which MMIO
accesses cause an exception. Fix it by setting the bridge enable bit.
This change is ported from the linux pcie-xilinx driver.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 drivers/pci/pcie_xilinx.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Michal Simek Nov. 2, 2023, 9:13 a.m. UTC | #1 
On 11/2/23 09:23, Mayuresh Chitale wrote:
> 
> The host bridge MMIO region is disabled by default due to which MMIO
> accesses cause an exception. Fix it by setting the bridge enable bit.
> This change is ported from the linux pcie-xilinx driver.
> 
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
>   drivers/pci/pcie_xilinx.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
> index 20b630027f..d1fbd40175 100644
> --- a/drivers/pci/pcie_xilinx.c
> +++ b/drivers/pci/pcie_xilinx.c
> @@ -25,6 +25,8 @@ struct xilinx_pcie {
>   /* Register definitions */
>   #define XILINX_PCIE_REG_PSCR		0x144
>   #define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
> +#define XILINX_PCIE_REG_RPSC		0x148
> +#define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
>   
>   /**
>    * pcie_xilinx_link_up() - Check whether the PCIe link is up
> @@ -142,6 +144,7 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev)
>   	struct xilinx_pcie *pcie = dev_get_priv(dev);
>   	fdt_addr_t addr;
>   	fdt_size_t size;
> +	u32 rpsc;
>   
>   	addr = dev_read_addr_size(dev, &size);
>   	if (addr == FDT_ADDR_T_NONE)
> @@ -149,6 +152,11 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev)
>   
>   	pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE);
>   
> +	/* Enable the Bridge enable bit */
> +	rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
> +	rpsc |= XILINX_PCIE_REG_RPSC_BEN;
> +	__raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
> +
>   	return 0;
>   }
>   

This looks good but depends on previous patch in this series that's why
Reviewed-by: Michal Simek <michal.simek@amd.com>

Thanks,
Michal
diff mbox series

Patch

diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index 20b630027f..d1fbd40175 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -25,6 +25,8 @@  struct xilinx_pcie {
 /* Register definitions */
 #define XILINX_PCIE_REG_PSCR		0x144
 #define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
+#define XILINX_PCIE_REG_RPSC		0x148
+#define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
 
 /**
  * pcie_xilinx_link_up() - Check whether the PCIe link is up
@@ -142,6 +144,7 @@  static int pcie_xilinx_of_to_plat(struct udevice *dev)
 	struct xilinx_pcie *pcie = dev_get_priv(dev);
 	fdt_addr_t addr;
 	fdt_size_t size;
+	u32 rpsc;
 
 	addr = dev_read_addr_size(dev, &size);
 	if (addr == FDT_ADDR_T_NONE)
@@ -149,6 +152,11 @@  static int pcie_xilinx_of_to_plat(struct udevice *dev)
 
 	pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE);
 
+	/* Enable the Bridge enable bit */
+	rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+	rpsc |= XILINX_PCIE_REG_RPSC_BEN;
+	__raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC);
+
 	return 0;
 }