| Message ID | 20230804093354.6619-4-jonas@kwiboo.se |
|---|---|
| State | Accepted |
| Commit | ff46cd56318015133e92140b31083eab68e701f7 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: Clock fixes for RK3568 | expand |
On 8/4/23 12:33, Jonas Karlman wrote: > The clock driver for RK3568 does not include support for UART clocks in > SPL. This result in the following message with high enough loglevel. > > ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 > > Fix this by including support for UART clocks in SPL. > > Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- Something like this it's also done for the 3588, and I still have not figured out why. When the rk3588 clock driver was added, I commented on this, but the result was just that the 'clock not found' message was removed. I am happy that you found some time to do these changes Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
On 2023-08-04 12:05, Eugen Hristev wrote: > On 8/4/23 12:33, Jonas Karlman wrote: >> The clock driver for RK3568 does not include support for UART clocks in >> SPL. This result in the following message with high enough loglevel. >> >> ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 The change to include UART clocks in SPL does not fix above warning message. Instead the patch at [1] fixes this warning. This change is however fixing that the ns16550_serial can get the UART clock rate from clock instead of falling back on clock-frequency property in DT. Will re-spin with an updated commit message. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230805111041.750550-1-jonas@kwiboo.se/ Regards, Jonas >> >> Fix this by including support for UART clocks in SPL. >> >> Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> >> --- > > Something like this it's also done for the 3588, and I still have not > figured out why. When the rk3588 clock driver was added, I commented on > this, but the result was just that the 'clock not found' message was > removed. > > I am happy that you found some time to do these changes > > Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> >
On 2023/8/4 17:33, Jonas Karlman wrote: > The clock driver for RK3568 does not include support for UART clocks in > SPL. This result in the following message with high enough loglevel. > > ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 > > Fix this by including support for UART clocks in SPL. > > Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/clk/rockchip/clk_rk3568.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c > index dab254d4d115..dabc7e70dd5a 100644 > --- a/drivers/clk/rockchip/clk_rk3568.c > +++ b/drivers/clk/rockchip/clk_rk3568.c > @@ -2189,6 +2189,7 @@ static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv, > > return rk3568_rkvdec_get_clk(priv, clk_id); > } > +#endif > > static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id) > { > @@ -2324,7 +2325,6 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv, > > return rk3568_uart_get_rate(priv, clk_id); > } > -#endif > > static ulong rk3568_clk_get_rate(struct clk *clk) > { > @@ -2463,6 +2463,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk) > case TCLK_WDT_NS: > rate = OSC_HZ; > break; > +#endif > case SCLK_UART1: > case SCLK_UART2: > case SCLK_UART3: > @@ -2474,7 +2475,6 @@ static ulong rk3568_clk_get_rate(struct clk *clk) > case SCLK_UART9: > rate = rk3568_uart_get_rate(priv, clk->id); > break; > -#endif > case ACLK_SECURE_FLASH: > case ACLK_CRYPTO_NS: > case HCLK_SECURE_FLASH: > @@ -2648,6 +2648,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) > case TCLK_WDT_NS: > ret = OSC_HZ; > break; > +#endif > case SCLK_UART1: > case SCLK_UART2: > case SCLK_UART3: > @@ -2659,7 +2660,6 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) > case SCLK_UART9: > ret = rk3568_uart_set_rate(priv, clk->id, rate); > break; > -#endif > case ACLK_SECURE_FLASH: > case ACLK_CRYPTO_NS: > case HCLK_SECURE_FLASH:
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index dab254d4d115..dabc7e70dd5a 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -2189,6 +2189,7 @@ static ulong rk3568_rkvdec_set_clk(struct rk3568_clk_priv *priv, return rk3568_rkvdec_get_clk(priv, clk_id); } +#endif static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id) { @@ -2324,7 +2325,6 @@ static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv, return rk3568_uart_get_rate(priv, clk_id); } -#endif static ulong rk3568_clk_get_rate(struct clk *clk) { @@ -2463,6 +2463,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case TCLK_WDT_NS: rate = OSC_HZ; break; +#endif case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: @@ -2474,7 +2475,6 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case SCLK_UART9: rate = rk3568_uart_get_rate(priv, clk->id); break; -#endif case ACLK_SECURE_FLASH: case ACLK_CRYPTO_NS: case HCLK_SECURE_FLASH: @@ -2648,6 +2648,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case TCLK_WDT_NS: ret = OSC_HZ; break; +#endif case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: @@ -2659,7 +2660,6 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case SCLK_UART9: ret = rk3568_uart_set_rate(priv, clk->id, rate); break; -#endif case ACLK_SECURE_FLASH: case ACLK_CRYPTO_NS: case HCLK_SECURE_FLASH:
The clock driver for RK3568 does not include support for UART clocks in SPL. This result in the following message with high enough loglevel. ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 Fix this by including support for UART clocks in SPL. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/clk/rockchip/clk_rk3568.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)