| Message ID | 20230628081530.3184607-1-uwu@icenowy.me |
|---|---|
| State | RFC |
| Delegated to: | Andes |
| Headers | show |
| Series | [RFC] riscv: sifive: fu70: downclock CPU clock for stability | expand |
On Wed, 28 Jun 2023, Icenowy Zheng wrote: > When building the package `rustc` for AOSC OS on HiFive Unmatched, > random SIGSEGV prevents the package from getting correctly built. > Downclocking the CPU PLL clock seems to allow rustc to be built, > although taking much more time. > > Downclock the CPU PLL frequency for stability. FYI, I've been observing occasional (less than 1 bit per 10GiB of data moved) single-bit data corruption on DRAM writes with my HiFive Unmatched, but your change does not appear to make any difference with my system. FWIW, given the price and amount of DRAM used I think it makes no sense to build computers equipped with a DRAM subsystem without ECC nowadays. Maciej
在 2023-07-12星期三的 14:13 +0100，Maciej W. Rozycki写道： > On Wed, 28 Jun 2023, Icenowy Zheng wrote: > > > When building the package `rustc` for AOSC OS on HiFive Unmatched, > > random SIGSEGV prevents the package from getting correctly built. > > Downclocking the CPU PLL clock seems to allow rustc to be built, > > although taking much more time. > > > > Downclock the CPU PLL frequency for stability. > > FYI, I've been observing occasional (less than 1 bit per 10GiB of > data > moved) single-bit data corruption on DRAM writes with my HiFive > Unmatched, > but your change does not appear to make any difference with my > system. > > FWIW, given the price and amount of DRAM used I think it makes no > sense > to build computers equipped with a DRAM subsystem without ECC > nowadays. Well the HiFive Unmatched board looks like it has a DRAM chip for ECC, but whether this is activated is not known... > > Maciej
On Thu, 13 Jul 2023, Icenowy Zheng wrote: > > FWIW, given the price and amount of DRAM used I think it makes no > > sense > > to build computers equipped with a DRAM subsystem without ECC > > nowadays. > > Well the HiFive Unmatched board looks like it has a DRAM chip for ECC, > but whether this is activated is not known... I don't think so. According to documentation and visual inspection of the board it has eight 2Gx8 DRAM chips. For ECC it would have to have nine 2Gx8 chips. Maciej
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index 706224b384..6b80cab588 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -8,7 +8,7 @@ / { cpus { assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>; - assigned-clock-rates = <1200000000>; + assigned-clock-rates = <988000000>; bootph-pre-ram; cpu0: cpu@0 { clocks = <&prci FU740_PRCI_CLK_COREPLL>;
When building the package `rustc` for AOSC OS on HiFive Unmatched, random SIGSEGV prevents the package from getting correctly built. Downclocking the CPU PLL clock seems to allow rustc to be built, although taking much more time. Downclock the CPU PLL frequency for stability. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> --- arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)