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[v1,11/17] riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC

Message ID 20221212025020.23778-12-yanhong.wang@starfivetech.com
State Superseded
Delegated to: Andes
Headers show
Series Basic StarFive JH7110 RISC-V SoC support | expand

Commit Message

Yanhong Wang Dec. 12, 2022, 2:50 a.m. UTC 
Add Kconfig to select the basic functions for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
---
 arch/riscv/cpu/jh7110/Kconfig | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 arch/riscv/cpu/jh7110/Kconfig
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Patch

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
new file mode 100644
index 0000000000..3f145415eb
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -0,0 +1,28 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+config STARFIVE_JH7110
+	bool
+	select ARCH_EARLY_INIT_R
+	select CLK_JH7110
+	select CPU
+	select CPU_RISCV
+	select RAM
+	select RESET_JH7110
+	select SUPPORT_SPL
+	select SPL_RAM if SPL
+	select SPL_STARFIVE_DDR
+	select PINCTRL_STARFIVE_JH7110
+	imply MMC
+	imply MMC_BROKEN_CD
+	imply MMC_SPI
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CACHE
+	imply SIFIVE_CCACHE
+	imply SMP
+	imply SPI
+	imply SPL_CPU
+	imply SPL_LOAD_FIT
+	imply SPL_OPENSBI
+	imply SPL_SIFIVE_CLINT