| Message ID | 20220215161611.1563067-5-Niklas.Cassel@wdc.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | canaan k210 SoC fixes | expand |
On 2/15/22 11:16 AM, Niklas Cassel wrote: > From: Damien Le Moal <damien.lemoal@opensource.wdc.com> > > The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is documented > to have a 32 word deep TX and RX FIFO, which spi_hw_init() detects. > However, when the RX FIFO is filled up to 32 entries (RXFLR = 32), an > RX FIFO overrun error occurs. Avoid this problem by force setting > fifo_len to 31. > > Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > --- > drivers/spi/designware_spi.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c > index 9200efced9..f9b19a5ea4 100644 > --- a/drivers/spi/designware_spi.c > +++ b/drivers/spi/designware_spi.c > @@ -194,6 +194,20 @@ static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv) > return 0; > } > > +static int dw_spi_apb_k210_init(struct udevice *bus, struct dw_spi_priv *priv) > +{ > + /* > + * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is > + * documented to have a 32 word deep TX and RX FIFO, which > + * spi_hw_init() detects. However, when the RX FIFO is filled up to > + * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid > + * this problem by force setting fifo_len to 31. > + */ > + priv->fifo_len = 31; > + > + return dw_spi_apb_init(bus, priv); > +} > + > static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv) > { > priv->max_xfer = 32; > @@ -758,7 +772,7 @@ static const struct udevice_id dw_spi_ids[] = { > */ > { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init }, > { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init }, > - { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_init }, > + { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_k210_init}, > { .compatible = "canaan,k210-ssi", .data = (ulong)dw_spi_dwc_init }, > { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init }, > { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init }, > Reviewed-by: Sean Anderson <seanga2@gmail.com>
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 9200efced9..f9b19a5ea4 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -194,6 +194,20 @@ static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv) return 0; } +static int dw_spi_apb_k210_init(struct udevice *bus, struct dw_spi_priv *priv) +{ + /* + * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is + * documented to have a 32 word deep TX and RX FIFO, which + * spi_hw_init() detects. However, when the RX FIFO is filled up to + * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid + * this problem by force setting fifo_len to 31. + */ + priv->fifo_len = 31; + + return dw_spi_apb_init(bus, priv); +} + static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv) { priv->max_xfer = 32; @@ -758,7 +772,7 @@ static const struct udevice_id dw_spi_ids[] = { */ { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init }, { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init }, - { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_init }, + { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_k210_init}, { .compatible = "canaan,k210-ssi", .data = (ulong)dw_spi_dwc_init }, { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init }, { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },