| Message ID | 20220214052845.40610-1-raj.khem@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: fix build with binutils 2.38 | expand |
Hi Khem, On Sun, Feb 13, 2022 at 09:28:45PM -0800, Khem Raj wrote: > From version 2.38, binutils default to ISA spec version 20191213. This > means that the csr read/write (csrr*/csrw*) instructions and fence.i > instruction has separated from the `I` extension, become two standalone > extensions: Zicsr and Zifencei. > > The fix is to specify those extensions explicitly in -march. However as > older binutils version do not support this, we first need to detect > that. > > Fixes > arch/riscv/lib/cache.c: Assembler messages: > arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i' > > Signed-off-by: Khem Raj <raj.khem@gmail.com> > Cc: Rick Chen <rick@andestech.com> > Cc: Leo <ycliang@andestech.com> Thanks for sending the patch. As Alexandre has already sent out a patch to solve this problem first, (https://patchwork.ozlabs.org/project/uboot/patch/20220128134713.2322800-1-alexandre.ghiti@canonical.com/) we'd go with this patch and we welcome your future patches to improve RISC-V U-Boot. Best regards, Leo
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..e6fe1fc02b 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,12 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C)_zicsr_zifencei) +zicsr_zifencei-$(toolchain-need-zicsr-zifencei) := _zicsr_zifencei + +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C)$(zicsr_zifencei-y) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. The fix is to specify those extensions explicitly in -march. However as older binutils version do not support this, we first need to detect that. Fixes arch/riscv/lib/cache.c: Assembler messages: arch/riscv/lib/cache.c:12: Error: unrecognized opcode `fence.i' Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Rick Chen <rick@andestech.com> Cc: Leo <ycliang@andestech.com> --- arch/riscv/Makefile | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)