diff mbox series

soc: soc_ti_k3: update j721e revision numbering

Message ID 20220126220733.6356-1-bb@ti.com
State Accepted
Delegated to: Tom Rini
Headers show
Series soc: soc_ti_k3: update j721e revision numbering | expand

Commit Message

Bryan Brattlof Jan. 26, 2022, 10:07 p.m. UTC
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.

CC: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
---
 drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
 1 file changed, 27 insertions(+), 13 deletions(-)

Comments

Bryan Brattlof Jan. 27, 2022, 7:01 p.m. UTC | #1
Sorry Tom!

On this day, January 26, 2022, thus sayeth Bryan Brattlof:
> There is a 4 bit VARIANT number inside the JTAGID register that TI
> increments any time a new variant for a chip is produced. Each
> family of TI's SoCs uses a different versioning scheme based off
> that VARIANT number.
> 
> CC: Dave Gerlach <d-gerlach@ti.com>
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> ---
>  drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
>  1 file changed, 27 insertions(+), 13 deletions(-)
>

I should have sent this to you.
~Bryan
Tom Rini Jan. 27, 2022, 7:10 p.m. UTC | #2
On Thu, Jan 27, 2022 at 01:01:33PM -0600, Bryan Brattlof wrote:

> Sorry Tom!
> 
> On this day, January 26, 2022, thus sayeth Bryan Brattlof:
> > There is a 4 bit VARIANT number inside the JTAGID register that TI
> > increments any time a new variant for a chip is produced. Each
> > family of TI's SoCs uses a different versioning scheme based off
> > that VARIANT number.
> > 
> > CC: Dave Gerlach <d-gerlach@ti.com>
> > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > ---
> >  drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++-------------
> >  1 file changed, 27 insertions(+), 13 deletions(-)
> >
> 
> I should have sent this to you.

I saw on the list, thanks.
Tom Rini Feb. 8, 2022, 5:32 p.m. UTC | #3
On Wed, Jan 26, 2022 at 04:07:33PM -0600, Bryan Brattlof wrote:

> There is a 4 bit VARIANT number inside the JTAGID register that TI
> increments any time a new variant for a chip is produced. Each
> family of TI's SoCs uses a different versioning scheme based off
> that VARIANT number.
> 
> CC: Dave Gerlach <d-gerlach@ti.com>
> Signed-off-by: Bryan Brattlof <bb@ti.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 9abed7d490a2c..7a126857cd709 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -15,9 +15,6 @@ 
 #define J7200			0xbb6d
 #define AM64X			0xbb38
 
-#define REV_SR1_0		0
-#define REV_SR2_0		1
-
 #define JTAG_ID_VARIANT_SHIFT	28
 #define JTAG_ID_VARIANT_MASK	(0xf << 28)
 #define JTAG_ID_PARTNO_SHIFT	12
@@ -55,25 +52,42 @@  static const char *get_family_string(u32 idreg)
 	return family;
 }
 
+static char *j721e_rev_string_map[] = {
+	"1.0", "1.1",
+};
+
+static char *am65x_rev_string_map[] = {
+	"1.0", "2.0",
+};
+
 static const char *get_rev_string(u32 idreg)
 {
-	const char *revision;
 	u32 rev;
+	u32 soc;
 
 	rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+	soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
-	switch (rev) {
-	case REV_SR1_0:
-		revision = "1.0";
-		break;
-	case REV_SR2_0:
-		revision = "2.0";
-		break;
+	switch (soc) {
+	case J721E:
+		if (rev > ARRAY_SIZE(j721e_rev_string_map))
+			goto bail;
+		return j721e_rev_string_map[rev];
+
+	case AM65X:
+		if (rev > ARRAY_SIZE(am65x_rev_string_map))
+			goto bail;
+		return am65x_rev_string_map[rev];
+
+	case AM64X:
+	case J7200:
 	default:
-		revision = "Unknown Revision";
+		if (!rev)
+			return "1.0";
 	};
 
-	return revision;
+bail:
+	return "Unknown Revision";
 }
 
 static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size)