| Message ID | 20211022142215.26484-6-pali@kernel.org |
|---|---|
| State | Accepted |
| Commit | 79b4eb21b486e30b29c5ba3038ea6ba0e1968458 |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | pci: pci_mvebu: Fix access to config space and PCIe Root Port | expand |
On 22.10.21 16:22, Pali Rohár wrote: > PCI Bridge is always accessible also when link is down. So move detection > of link up from mvebu_pcie_of_to_plat() function to mvebu_pcie_valid_addr() > function which is used when accessing PCI config space. > > Signed-off-by: Pali Rohár <pali@kernel.org> > Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > drivers/pci/pci_mvebu.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) > > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c > index 4b8e56f22dfa..40b8a57bbe1e 100644 > --- a/drivers/pci/pci_mvebu.c > +++ b/drivers/pci/pci_mvebu.c > @@ -138,6 +138,10 @@ static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, > if (busno == pcie->first_busno && (dev != 0 || func != 0)) > return false; > > + /* Access to other buses is possible when link is up */ > + if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie)) > + return false; > + > /* On secondary bus can be only one PCIe device */ > if (busno == pcie->sec_busno && dev != 0) > return false; > @@ -369,9 +373,6 @@ static int mvebu_pcie_probe(struct udevice *dev) > struct pci_controller *hose = dev_get_uclass_priv(ctlr); > u32 reg; > > - debug("%s: PCIe %d.%d - up, base %08x\n", __func__, > - pcie->port, pcie->lane, (u32)pcie->base); > - > /* > * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) > * because default value is Memory controller (0x508000) which > @@ -603,13 +604,6 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev) > if (ret < 0) > goto err; > > - /* Check link and skip ports that have no link */ > - if (!mvebu_pcie_link_up(pcie)) { > - debug("%s: %s - down\n", __func__, pcie->name); > - ret = -ENODEV; > - goto err; > - } > - > return 0; > > err: > Viele Grüße, Stefan
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 4b8e56f22dfa..40b8a57bbe1e 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -138,6 +138,10 @@ static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, if (busno == pcie->first_busno && (dev != 0 || func != 0)) return false; + /* Access to other buses is possible when link is up */ + if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie)) + return false; + /* On secondary bus can be only one PCIe device */ if (busno == pcie->sec_busno && dev != 0) return false; @@ -369,9 +373,6 @@ static int mvebu_pcie_probe(struct udevice *dev) struct pci_controller *hose = dev_get_uclass_priv(ctlr); u32 reg; - debug("%s: PCIe %d.%d - up, base %08x\n", __func__, - pcie->port, pcie->lane, (u32)pcie->base); - /* * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) * because default value is Memory controller (0x508000) which @@ -603,13 +604,6 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev) if (ret < 0) goto err; - /* Check link and skip ports that have no link */ - if (!mvebu_pcie_link_up(pcie)) { - debug("%s: %s - down\n", __func__, pcie->name); - ret = -ENODEV; - goto err; - } - return 0; err: