Message ID | 20211019104049.v3.2.Iea14d1fdd56dcd7674565d29b827c242301a0600@changeid |
---|---|
State | Accepted |
Commit | c4eef59faab6ae4ecb1beae6d4391b0889bc3ff3 |
Delegated to: | Tom Rini |
Headers | show |
Series | [v3,1/2] nvme: Enable FUA | expand |
On Tue, Oct 19, 2021 at 10:40:54AM +0800, Jon Lin wrote: > Consulting to "NVM Express® Base Specification, revision 2.0". > > If more PRP List pages are required, then the last entry of > the PRP List contains the Page Base Address of the next PRP > List page. The next PRP List page shall be memory page aligned. > > Signed-off-by: Jon Lin <jon.lin@rock-chips.com> > Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Applied to u-boot/next, thanks!
diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 9623c896a1..22ded626a5 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -100,7 +100,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, } nprps = DIV_ROUND_UP(length, page_size); - num_pages = DIV_ROUND_UP(nprps, prps_per_page); + num_pages = DIV_ROUND_UP(nprps + 1, prps_per_page); if (nprps > dev->prp_entry_num) { free(dev->prp_pool); @@ -119,10 +119,11 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, prp_pool = dev->prp_pool; i = 0; while (nprps) { - if (i == ((page_size >> 3) - 1)) { - *(prp_pool + i) = cpu_to_le64((ulong)prp_pool + + if (i == prps_per_page) { + *(prp_pool + i) = *(prp_pool + i - 1); + *(prp_pool + i - 1) = cpu_to_le64((ulong)prp_pool + page_size); - i = 0; + i = 1; prp_pool += page_size; } *(prp_pool + i++) = cpu_to_le64(dma_addr);