diff mbox series

[v2,4/5] clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write

Message ID 20210907221658.12428-5-d-gerlach@ti.com
State Accepted
Commit d3c56e2a823caa1e2d09daccd1b0d8a529d8df69
Delegated to: Tom Rini
Headers show
Series arm: mach-k3: Fixes for j721e/j7200 clock data and drivers | expand

Commit Message

Dave Gerlach Sept. 7, 2021, 10:16 p.m. UTC 
There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.

Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.

Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 drivers/clk/ti/clk-k3-pll.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Tom Rini Sept. 17, 2021, 10:53 p.m. UTC | #1 
On Tue, Sep 07, 2021 at 05:16:57PM -0500, Dave Gerlach wrote:

> There are three different divider values in the DIV_CTRL register
> controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
> function writes the entire register when programming plld, even though
> plld only resides in the lower 6 bits.
> 
> Change the plld programming to read-modify-write to only affect the
> relevant bits for plld and to preserve the other two divider values
> present in the upper 16 bits, otherwise they will always get set to zero
> when programming plld.
> 
> Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL")
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
index bf2407a020a3..bf762c558ef0 100644
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -2,7 +2,7 @@ 
 /*
  * Texas Instruments K3 SoC PLL clock driver
  *
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
  *	Tero Kristo <t-kristo@ti.com>
  */
 
@@ -122,6 +122,7 @@  static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
 	unsigned long pllm;
 	u32 pllfm = 0;
 	unsigned long plld;
+	u32 div_ctrl;
 	u32 rem;
 	int shift;
 
@@ -175,7 +176,15 @@  static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
 
 	writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
 	writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
-	writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+	/*
+	 * div_ctrl register contains other divider values, so rmw
+	 * only plld and leave existing values alone
+	 */
+	div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
+	div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+	div_ctrl |= plld;
+	writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
 
 	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
 	ctrl |= PLL_16FFT_CTRL_PLL_EN;