| Message ID | 20210731122256.6546-3-pali@kernel.org |
|---|---|
| State | Accepted |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | arm: mvebu: Automatically detect CONFIG_SYS_TCLK | expand |
On 31.07.21 14:22, Pali Rohár wrote: > Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. > Use this information instead of manual configuration in every board file. > > Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan > --- > arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ > include/configs/db-88f6720.h | 1 - > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h > index cb323aa59a76..eb6906ad8027 100644 > --- a/arch/arm/mach-mvebu/include/mach/soc.h > +++ b/arch/arm/mach-mvebu/include/mach/soc.h > @@ -145,6 +145,9 @@ > > #define BOOT_FROM_UART 0x30 > #define BOOT_FROM_SPI 0x38 > + > +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ > + 200000000 : 166000000) > #elif defined(CONFIG_ARMADA_38X) > /* SAR values for Armada 38x */ > #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) > diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h > index cbb9270f9327..67d8cd42d1c2 100644 > --- a/include/configs/db-88f6720.h > +++ b/include/configs/db-88f6720.h > @@ -15,7 +15,6 @@ > * for DDR ECC byte filling in the SPL before loading the main > * U-Boot into it. > */ > -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ > > /* I2C */ > #define CONFIG_SYS_I2C > Viele Grüße, Stefan
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index cb323aa59a76..eb6906ad8027 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -145,6 +145,9 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ + 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index cbb9270f9327..67d8cd42d1c2 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* I2C */ #define CONFIG_SYS_I2C
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> --- arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ include/configs/db-88f6720.h | 1 - 2 files changed, 3 insertions(+), 1 deletion(-)