diff mbox series

clock_imx8mq: Added 66 MHz support for QSPI

Message ID 20210624011252.4968-1-tykwon@m2i.co.kr
State New
Delegated to: Stefano Babic
Headers show
Series clock_imx8mq: Added 66 MHz support for QSPI | expand

Commit Message

권태영 June 24, 2021, 1:12 a.m. UTC
At the current clock setting, the maximum clock for QSPI is 25 MHz.
In my case I use M-RAM which supports up to 100 MHz for QSPI, and with
this change the QSPI can be clocked up to 66 MHz.

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
---
 arch/arm/mach-imx/imx8m/clock_imx8mq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

권태영 June 24, 2021, 2:18 a.m. UTC | #1
> Hi Kwon,
>
> On Wed, Jun 23, 2021 at 10:13 PM Kwon Tae-young <tykwon@m2i.co.kr> wrote:
> >
> > At the current clock setting, the maximum clock for QSPI is 25 MHz.
> > In my case I use M-RAM which supports up to 100 MHz for QSPI, and with 
> > this change the QSPI can be clocked up to 66 MHz.
> >
> > Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
> > ---
> >  arch/arm/mach-imx/imx8m/clock_imx8mq.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c 
> > b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
> > index 8fecc60ecb..47b4a8f01f 100644
> > --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
> > @@ -473,11 +473,11 @@ int set_clk_qspi(void)  {
> >         /*
> >          * set qspi root
> > -        * sys pll1 100M
> > +        * sys pll1 266M
> >          */
> >         clock_enable(CCGR_QSPI, 0);
> >         clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
> > -                            CLK_ROOT_SOURCE_SEL(7));
> > +                            CLK_ROOT_SOURCE_SEL(5));
>
> It seems there is 'divide-by 4' being set somewhere.
>
> What if you use CLK_ROOT_SOURCE_SEL(1) instead?
>
> This selects SYS_PLL1_400MHz as the QSPI parent clock and should give you the 100MHz QSPI clock that you need.

The clocks I tested are as follows.
CLK_ROOT_SOURCE_SEL(0): 6.25 Mhz
CLK_ROOT_SOURCE_SEL(1): 100 Mhz
CLK_ROOT_SOURCE_SEL(2): 100 Mhz
CLK_ROOT_SOURCE_SEL(3): 125 Mhz
CLK_ROOT_SOURCE_SEL(4): 90.36 Mhz
CLK_ROOT_SOURCE_SEL(5): 66.69 Mhz
CLK_ROOT_SOURCE_SEL(6): 6.25 Mhz
CLK_ROOT_SOURCE_SEL(7): 25 Mhz

However, my board only passed the load test up to 66MHz.
Should I change it to CLK_ROOT_SOURCE_SEL(1) and submit the patch?
diff mbox series

Patch

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 8fecc60ecb..47b4a8f01f 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -473,11 +473,11 @@  int set_clk_qspi(void)
 {
 	/*
 	 * set qspi root
-	 * sys pll1 100M
+	 * sys pll1 266M
 	 */
 	clock_enable(CCGR_QSPI, 0);
 	clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
-			     CLK_ROOT_SOURCE_SEL(7));
+			     CLK_ROOT_SOURCE_SEL(5));
 	clock_enable(CCGR_QSPI, 1);
 
 	return 0;