| Message ID | 20210114032957.483086-14-sjg@chromium.org |
|---|---|
| State | Accepted |
| Commit | 0751cda5745efcff1a4bfc70c42bab380901b0b8 |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | Various minor clean-ups and improvements | expand |
On 1/14/21 12:29 PM, Simon Glass wrote: > Add a node for this so we can indicate that it is does not require any > ACPI code. > > Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung > --- > > arch/x86/dts/chromebook_coral.dts | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts > index 965f59276af..bfbdd517d1f 100644 > --- a/arch/x86/dts/chromebook_coral.dts > +++ b/arch/x86/dts/chromebook_coral.dts > @@ -569,6 +569,12 @@ > acpi,name = "SDCD"; > }; > > + emmc: emmc@1c,0 { > + reg = <0x0000e000 0 0 0 0>; > + compatible = "intel,apl-emmc"; > + non-removable; > + }; > + > pch: pch@1f,0 { > reg = <0x0000f800 0 0 0 0>; > compatible = "intel,apl-pch"; >
On Thu, Jan 14, 2021 at 11:30 AM Simon Glass <sjg@chromium.org> wrote: > > Add a node for this so we can indicate that it is does not require any > ACPI code. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/dts/chromebook_coral.dts | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Mon, Feb 1, 2021 at 2:11 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Thu, Jan 14, 2021 at 11:30 AM Simon Glass <sjg@chromium.org> wrote: > > > > Add a node for this so we can indicate that it is does not require any > > ACPI code. > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > --- > > > > arch/x86/dts/chromebook_coral.dts | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> applied to u-boot-x86, thanks!
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965f59276af..bfbdd517d1f 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -569,6 +569,12 @@ acpi,name = "SDCD"; }; + emmc: emmc@1c,0 { + reg = <0x0000e000 0 0 0 0>; + compatible = "intel,apl-emmc"; + non-removable; + }; + pch: pch@1f,0 { reg = <0x0000f800 0 0 0 0>; compatible = "intel,apl-pch";
Add a node for this so we can indicate that it is does not require any ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/dts/chromebook_coral.dts | 6 ++++++ 1 file changed, 6 insertions(+)