diff mbox series

[v2,6/9] armv8: layerscape: don't initialize GIC in SPL

Message ID 20201118164602.22518-7-michael@walle.cc
State Accepted
Commit 8084e918bca8fa2ecf226a5eac5ea064d669b301
Delegated to: Tom Rini
Headers show
Series spl: atf: add support for LOAD_IMAGE_V2 | expand

Commit Message

Michael Walle Nov. 18, 2020, 4:45 p.m. UTC
The BL31 expects the GIC to be uninitialized. Thus, if we are loading
the BL31 by the SPL we must not initialize it. If u-boot is loaded by
the SPL directly, it will initialize the GIC again (in the same
lowlevel_init()).

This was tested on a custom board with SPL loading the BL31 and jumping
to u-boot as BL33 as well as loading u-boot directly by the SPL. In case
the ATF BL1/BL2 is used, this patch won't change anything, because no
SPL is used at all.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
 1 file changed, 2 insertions(+)

Comments

Tom Rini Dec. 7, 2020, 10:20 p.m. UTC | #1
On Wed, Nov 18, 2020 at 05:45:59PM +0100, Michael Walle wrote:

> The BL31 expects the GIC to be uninitialized. Thus, if we are loading
> the BL31 by the SPL we must not initialize it. If u-boot is loaded by
> the SPL directly, it will initialize the GIC again (in the same
> lowlevel_init()).
> 
> This was tested on a custom board with SPL loading the BL31 and jumping
> to u-boot as BL33 as well as loading u-boot directly by the SPL. In case
> the ATF BL1/BL2 is used, this patch won't change anything, because no
> SPL is used at all.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index a519f6ed67..d8803738f1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -192,6 +192,7 @@  ENTRY(lowlevel_init)
 #endif
 
 	/* Initialize GIC Secure Bank Status */
+#if !defined(CONFIG_SPL_BUILD)
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 	branch_if_slave x0, 1f
 	bl	get_gic_offset
@@ -205,6 +206,7 @@  ENTRY(lowlevel_init)
 	bl	gic_init_secure_percpu
 #endif
 #endif
+#endif
 
 100:
 	branch_if_master x0, x1, 2f