Message ID | 20200720033221.nc2oqa4bzzv2jtcu@proprietary-killer |
---|---|
State | Changes Requested |
Delegated to: | Kever Yang |
Headers | show |
Series | rk3399-gru-kevin: issues on bringup | expand |
Hi Marty, On Sun, 19 Jul 2020 at 21:33, Marty E. Plummer <hanetzer@startmail.com> wrote: > > Greetings. > > I've been working on u-boot for rk3399-gru-kevin, Samsung Chromebook > Plus. In theory it should be fairly similar to the Bob chromebook, and > as such my work is largely based on it. Aside from some trivial changes, > and adding chromebook_kevin_defconfig (direct copy of bob's config, with > bob exchanged for kevin where apropriate) there is no major changes done > (current diff at bottom). > > After building, I prepare the image like this: > > =============== > $ ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img > # 0x60000 chosen from doc/board/rockchip/rockchip.rst:187 > $ dd if=idbloader.img of=start bs=$((0x60000)) conv=sync count=1 > $ cat u-boot.itb >> start > # 8mb spi flash > $ dd if=start of=flash.bin bs=$((1024*1024*8)) conv=sync count=1 > =============== > > and flash it from within a chromeos dev env with a servo, like this: > =============== > # power down > $ dut-control spi2_buf_en:on spi2_buf_on_flex_en:on spi2_vref:pp3300 cold_reset:on > # flash > $ sudo flashrom -V --programmer ft2232_spi:type=google-servo-v2 -w flash.bin > # power up > $ dut-control spi2_buf_en:off spi2_buf_on_flex_en:off spi2_vref:off cold_reset:off > =============== > > But I do not get any more output than the following: (using the same ddr > config as bob, as it matches what coreboot's source tree has listed > during coreboot's bootup, to the best of my ability to tell. > src/mainboard/google/gru/sdram_params/sdram-lpddr3-generic-4GB-928.c > > =============== > Channel 0: LPDDR3, 933MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > Channel 1: LPDDR3, 933MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > 256B stride > 256B stride > > U-Boot SPL 2020.07-10102-g1c4b5038af-dirty (Jul 19 2020 - 22:04:50 -0500) > SPL: Unsupported Boot Device! > SPL: failed to boot from all boot devices > ### ERROR ### Please RESET the board ### > =============== > > Unsure where to proceed from here. I notice that when bob was originally > ported the chosen node had a u-boot,spl-boot-order property and the > config node had u-boot,spl-payload-offset, which is no more, perhaps > there is something to that? Did you check spl_boot_device()? Also take a look at the CONFIG_TARGET stuff in the code as it might speciy BOB but not KEVIN. Regards, Simon
On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > Hi Marty, > > Did you check spl_boot_device()? > After sending the initial email I noticed your binman work, which does some of the stuff I think I need. My current setup is as follows: diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cee10f533f..0e3e1cc553 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -122,6 +122,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-gru-kevin.dtb \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ diff --git a/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi new file mode 100644 index 0000000000..726f396f32 --- /dev/null +++ b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "rk3399-gru-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f9171..851083cd8a 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -14,6 +14,11 @@ config TARGET_CHROMEBOOK_BOB display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. +config TARGET_CHROMEBOOK_KEVIN + bool "Samsung Chromebook Plus (RK3399)" + select HAS_ROM + select ROCKCHIP_SPI_IMAGE + config TARGET_EVB_RK3399 bool "RK3399 evaluation board" help diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 4fda93b152..92b418a9cf 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -117,7 +117,7 @@ void board_debug_uart_init(void) #define GPIO0_BASE 0xff720000 #define PMUGRF_BASE 0xff320000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB +#if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; #endif @@ -139,7 +139,7 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) rk_setreg(&grf->io_vsel, 1 << 0); /* diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index f148d48b6a..a7a2bf10a1 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -55,7 +55,8 @@ u32 spl_boot_device(void) defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_BOB) + defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \ + defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) return BOOT_DEVICE_SPI; #endif if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig index 61f7bbca98..1455e1481d 100644 --- a/board/google/gru/Kconfig +++ b/board/google/gru/Kconfig @@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_KEVIN + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index 7dfbc3ac86..99ac658e32 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -14,7 +14,7 @@ void gru_dummy_function(int i) int board_early_init_f(void) { -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) int sum, i; /* diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig new file mode 100644 index 0000000000..ea975264b5 --- /dev/null +++ b/configs/chromebook_kevin_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xff1a0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h index 87cf351bab..331458c0e7 100644 --- a/include/dt-bindings/input/linux-event-codes.h +++ b/include/dt-bindings/input/linux-event-codes.h @@ -749,7 +749,8 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ +#define SW_MAX 0x10 #define SW_CNT (SW_MAX+1) /* > Also take a look at the CONFIG_TARGET stuff in the code as it might > speciy BOB but not KEVIN. Yeah. I worked that in. Currently, a rom which is built with these changes (assuming u-boot.rom is what I want for SPI booting; strange its only 4mb, aren't these devices 8mb flash?) I get no output at all over the servo, aside from the EC. > > Regards, > Simon
Hi Marty, On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > Hi Marty, > > > > Did you check spl_boot_device()? > > > After sending the initial email I noticed your binman work, which does > some of the stuff I think I need. My current setup is as follows: > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index cee10f533f..0e3e1cc553 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -122,6 +122,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ > rk3399-ficus.dtb \ > rk3399-firefly.dtb \ > rk3399-gru-bob.dtb \ > + rk3399-gru-kevin.dtb \ > rk3399-khadas-edge.dtb \ > rk3399-khadas-edge-captain.dtb \ > rk3399-khadas-edge-v.dtb \ > diff --git a/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi > new file mode 100644 > index 0000000000..726f396f32 > --- /dev/null > +++ b/arch/arm/dts/rk3399-gru-kevin-u-boot.dtsi > @@ -0,0 +1,7 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> > + */ > + > +#include "rk3399-gru-u-boot.dtsi" > +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" > diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig > index 17628f9171..851083cd8a 100644 > --- a/arch/arm/mach-rockchip/rk3399/Kconfig > +++ b/arch/arm/mach-rockchip/rk3399/Kconfig > @@ -14,6 +14,11 @@ config TARGET_CHROMEBOOK_BOB > display. It includes a Chrome OS EC (Cortex-M3) to provide access to > the keyboard and battery functions. > > +config TARGET_CHROMEBOOK_KEVIN > + bool "Samsung Chromebook Plus (RK3399)" > + select HAS_ROM > + select ROCKCHIP_SPI_IMAGE > + > config TARGET_EVB_RK3399 > bool "RK3399 evaluation board" > help > diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c > index 4fda93b152..92b418a9cf 100644 > --- a/arch/arm/mach-rockchip/rk3399/rk3399.c > +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c > @@ -117,7 +117,7 @@ void board_debug_uart_init(void) > #define GPIO0_BASE 0xff720000 > #define PMUGRF_BASE 0xff320000 > struct rk3399_grf_regs * const grf = (void *)GRF_BASE; > -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB > +#if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) > struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; > struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; > #endif > @@ -139,7 +139,7 @@ void board_debug_uart_init(void) > GRF_GPIO3B7_SEL_MASK, > GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); > #else > -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB > +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) > rk_setreg(&grf->io_vsel, 1 << 0); > > /* > diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c > index f148d48b6a..a7a2bf10a1 100644 > --- a/arch/arm/mach-rockchip/spl.c > +++ b/arch/arm/mach-rockchip/spl.c > @@ -55,7 +55,8 @@ u32 spl_boot_device(void) > defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ > defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ > defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \ > - defined(CONFIG_TARGET_CHROMEBOOK_BOB) > + defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \ > + defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) > return BOOT_DEVICE_SPI; > #endif > if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) > diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig > index 61f7bbca98..1455e1481d 100644 > --- a/board/google/gru/Kconfig > +++ b/board/google/gru/Kconfig > @@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy > def_bool y > > endif > + > +if TARGET_CHROMEBOOK_KEVIN > + > +config SYS_BOARD > + default "gru" > + > +config SYS_VENDOR > + default "google" > + > +config SYS_CONFIG_NAME > + default "gru" > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + > +endif > diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c > index 7dfbc3ac86..99ac658e32 100644 > --- a/board/google/gru/gru.c > +++ b/board/google/gru/gru.c > @@ -14,7 +14,7 @@ void gru_dummy_function(int i) > > int board_early_init_f(void) > { > -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB > +# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN) > int sum, i; > > /* > diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig > new file mode 100644 > index 0000000000..ea975264b5 > --- /dev/null > +++ b/configs/chromebook_kevin_defconfig > @@ -0,0 +1,82 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SYS_TEXT_BASE=0x00200000 > +CONFIG_SPL_GPIO_SUPPORT=y > +CONFIG_ENV_OFFSET=0x3F8000 > +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 > +CONFIG_SPL_TEXT_BASE=0xff8c2000 > +CONFIG_ROCKCHIP_RK3399=y > +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 > +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 > +# CONFIG_SPL_MMC_SUPPORT is not set > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_DEBUG_UART_BASE=0xff1a0000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > +CONFIG_DEBUG_UART=y > +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin" > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 > +CONFIG_SPL_SPI_LOAD=y > +CONFIG_CMD_BOOTZ=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_SF_TEST=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_TIME=y > +CONFIG_CMD_PMIC=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_CMD_LOG=y > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > +CONFIG_SPL_DM_SEQ_ALIAS=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_I2C_CROS_EC_TUNNEL=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_I2C_MUX=y > +CONFIG_DM_KEYBOARD=y > +CONFIG_CROS_EC_KEYB=y > +CONFIG_CROS_EC=y > +CONFIG_CROS_EC_SPI=y > +CONFIG_PWRSEQ=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_ROCKCHIP=y > +CONFIG_SF_DEFAULT_BUS=1 > +CONFIG_SF_DEFAULT_SPEED=20000000 > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_ROCKCHIP_SPI=y > +CONFIG_SYSRESET=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_HOST_ETHER=y > +CONFIG_USB_ETHER_ASIX=y > +CONFIG_USB_ETHER_ASIX88179=y > +CONFIG_USB_ETHER_MCS7830=y > +CONFIG_USB_ETHER_RTL8152=y > +CONFIG_USB_ETHER_SMSC95XX=y > +CONFIG_CMD_DHRYSTONE=y > +CONFIG_ERRNO_STR=y > diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h > index 87cf351bab..331458c0e7 100644 > --- a/include/dt-bindings/input/linux-event-codes.h > +++ b/include/dt-bindings/input/linux-event-codes.h > @@ -749,7 +749,8 @@ > #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ > #define SW_LINEIN_INSERT 0x0d /* set = inserted */ > #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ > -#define SW_MAX 0x0f > +#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ > +#define SW_MAX 0x10 > #define SW_CNT (SW_MAX+1) > > /* > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > speciy BOB but not KEVIN. > Yeah. I worked that in. > > Currently, a rom which is built with these changes (assuming u-boot.rom > is what I want for SPI booting; strange its only 4mb, aren't these > devices 8mb flash?) I get no output at all over the servo, aside from > the EC. I think it is only 4MB. I am not sure that I have a kevin. Did you try using the debug UART? Regards, Simon
On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > Hi Marty, > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > Hi Marty, > > > > > > Did you check spl_boot_device()? > > > > > After sending the initial email I noticed your binman work, which does > > some of the stuff I think I need. My current setup is as follows: > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > speciy BOB but not KEVIN. > > Yeah. I worked that in. > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > is what I want for SPI booting; strange its only 4mb, aren't these > > devices 8mb flash?) I get no output at all over the servo, aside from > > the EC. > > I think it is only 4MB. > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able to shove a 7.xmb kernel+initramfs into a coreboot image and flash it. I have to pad the u-boot.rom with dd to flash it. > I am not sure that I have a kevin. Did you try using the debug UART? > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked up, and using `socat READLINE /dev/pts/something`. I get no output, but the same chromiumos chroot with vanilla coreboot+depthcharge and hardware config does do output as expected. Perhaps I'm missing something simple. > Regards, > Simon
Hi Marty, On Fri, 31 Jul 2020 at 05:19, Marty E. Plummer <hanetzer@startmail.com> wrote: > > On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > > Hi Marty, > > > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > > Hi Marty, > > > > > > > > Did you check spl_boot_device()? > > > > > > > After sending the initial email I noticed your binman work, which does > > > some of the stuff I think I need. My current setup is as follows: > > > > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > > speciy BOB but not KEVIN. > > > Yeah. I worked that in. > > > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > > is what I want for SPI booting; strange its only 4mb, aren't these > > > devices 8mb flash?) I get no output at all over the servo, aside from > > > the EC. > > > > I think it is only 4MB. > > > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able > to shove a 7.xmb kernel+initramfs into a coreboot image and flash it. Well that's odd. Maybe Kevin got a larger device than gru? > > I have to pad the u-boot.rom with dd to flash it. > > I am not sure that I have a kevin. Did you try using the debug UART? > > > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked > up, and using `socat READLINE /dev/pts/something`. I get no output, but > the same chromiumos chroot with vanilla coreboot+depthcharge and > hardware config does do output as expected. > > Perhaps I'm missing something simple. Probably, it often is. But what?! I actually just found some old Chromebooks I didn't know i had, so I have a Kevin. If you push your tree somewhere I might be able to take a look this weekend. Regards, Simon
Hi Marty, On Fri, 31 Jul 2020 at 12:30, Simon Glass <sjg@chromium.org> wrote: > > Hi Marty, > > On Fri, 31 Jul 2020 at 05:19, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > > > Hi Marty, > > > > > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > > > Hi Marty, > > > > > > > > > > Did you check spl_boot_device()? > > > > > > > > > After sending the initial email I noticed your binman work, which does > > > > some of the stuff I think I need. My current setup is as follows: > > > > > > > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > > > speciy BOB but not KEVIN. > > > > Yeah. I worked that in. > > > > > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > > > is what I want for SPI booting; strange its only 4mb, aren't these > > > > devices 8mb flash?) I get no output at all over the servo, aside from > > > > the EC. > > > > > > I think it is only 4MB. > > > > > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able > > to shove a 7.xmb kernel+initramfs into a coreboot image and flash it. > > Well that's odd. Maybe Kevin got a larger device than gru? > > > > > I have to pad the u-boot.rom with dd to flash it. > > > I am not sure that I have a kevin. Did you try using the debug UART? > > > > > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked > > up, and using `socat READLINE /dev/pts/something`. I get no output, but > > the same chromiumos chroot with vanilla coreboot+depthcharge and > > hardware config does do output as expected. > > > > Perhaps I'm missing something simple. > > Probably, it often is. But what?! > > I actually just found some old Chromebooks I didn't know i had, so I > have a Kevin. If you push your tree somewhere I might be able to take > a look this weekend. I dug this out but I cannot get it to boot with the em100 emulator. I'll see if I can figure that out at some point. Sometimes I get serial garbage as well. It is surprising that the flash is 8MB when Gru is 4MB. Must have run out of room. Regards, Simon
Hi Marty, On Sun, 2 Aug 2020 at 21:02, Simon Glass <sjg@chromium.org> wrote: > > Hi Marty, > > On Fri, 31 Jul 2020 at 12:30, Simon Glass <sjg@chromium.org> wrote: > > > > Hi Marty, > > > > On Fri, 31 Jul 2020 at 05:19, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > > > > Hi Marty, > > > > > > > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > > > > Hi Marty, > > > > > > > > > > > > Did you check spl_boot_device()? > > > > > > > > > > > After sending the initial email I noticed your binman work, which does > > > > > some of the stuff I think I need. My current setup is as follows: > > > > > > > > > > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > > > > speciy BOB but not KEVIN. > > > > > Yeah. I worked that in. > > > > > > > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > > > > is what I want for SPI booting; strange its only 4mb, aren't these > > > > > devices 8mb flash?) I get no output at all over the servo, aside from > > > > > the EC. > > > > > > > > I think it is only 4MB. > > > > > > > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able > > > to shove a 7.xmb kernel+initramfs into a coreboot image and flash it. > > > > Well that's odd. Maybe Kevin got a larger device than gru? > > > > > > > > I have to pad the u-boot.rom with dd to flash it. > > > > I am not sure that I have a kevin. Did you try using the debug UART? > > > > > > > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked > > > up, and using `socat READLINE /dev/pts/something`. I get no output, but > > > the same chromiumos chroot with vanilla coreboot+depthcharge and > > > hardware config does do output as expected. > > > > > > Perhaps I'm missing something simple. > > > > Probably, it often is. But what?! > > > > I actually just found some old Chromebooks I didn't know i had, so I > > have a Kevin. If you push your tree somewhere I might be able to take > > a look this weekend. > > I dug this out but I cannot get it to boot with the em100 emulator. > I'll see if I can figure that out at some point. Sometimes I get > serial garbage as well. > > It is surprising that the flash is 8MB when Gru is 4MB. Must have run > out of room. Also I pushed the tree with your changes and one of mine here: https://github.com/sjg20/u-boot/tree/kevin Regards, SImon
Hi Marty, On Mon, 3 Aug 2020 at 07:49, Simon Glass <sjg@chromium.org> wrote: > > Hi Marty, > > On Sun, 2 Aug 2020 at 21:02, Simon Glass <sjg@chromium.org> wrote: > > > > Hi Marty, > > > > On Fri, 31 Jul 2020 at 12:30, Simon Glass <sjg@chromium.org> wrote: > > > > > > Hi Marty, > > > > > > On Fri, 31 Jul 2020 at 05:19, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > > > On Tue, Jul 28, 2020 at 12:58:30PM -0600, Simon Glass wrote: > > > > > Hi Marty, > > > > > > > > > > On Tue, 21 Jul 2020 at 21:07, Marty E. Plummer <hanetzer@startmail.com> wrote: > > > > > > > > > > > > On Tue, Jul 21, 2020 at 10:21:52AM -0600, Simon Glass wrote: > > > > > > > Hi Marty, > > > > > > > > > > > > > > Did you check spl_boot_device()? > > > > > > > > > > > > > After sending the initial email I noticed your binman work, which does > > > > > > some of the stuff I think I need. My current setup is as follows: > > > > > > > > > > > > > > > > > > > Also take a look at the CONFIG_TARGET stuff in the code as it might > > > > > > > speciy BOB but not KEVIN. > > > > > > Yeah. I worked that in. > > > > > > > > > > > > Currently, a rom which is built with these changes (assuming u-boot.rom > > > > > > is what I want for SPI booting; strange its only 4mb, aren't these > > > > > > devices 8mb flash?) I get no output at all over the servo, aside from > > > > > > the EC. > > > > > > > > > > I think it is only 4MB. > > > > > > > > > Nah, kevin is deffo 8mb flash chip. Otherwise I wouldn't have been able > > > > to shove a 7.xmb kernel+initramfs into a coreboot image and flash it. > > > > > > Well that's odd. Maybe Kevin got a larger device than gru? > > > > > > > > > > > I have to pad the u-boot.rom with dd to flash it. > > > > > I am not sure that I have a kevin. Did you try using the debug UART? > > > > > > > > > Yeah, assuming you mean `dut-control cpu_uart_pty` with a servo hooked > > > > up, and using `socat READLINE /dev/pts/something`. I get no output, but > > > > the same chromiumos chroot with vanilla coreboot+depthcharge and > > > > hardware config does do output as expected. > > > > > > > > Perhaps I'm missing something simple. > > > > > > Probably, it often is. But what?! > > > > > > I actually just found some old Chromebooks I didn't know i had, so I > > > have a Kevin. If you push your tree somewhere I might be able to take > > > a look this weekend. > > > > I dug this out but I cannot get it to boot with the em100 emulator. > > I'll see if I can figure that out at some point. Sometimes I get > > serial garbage as well. > > > > It is surprising that the flash is 8MB when Gru is 4MB. Must have run > > out of room. > > Also I pushed the tree with your changes and one of mine here: > > https://github.com/sjg20/u-boot/tree/kevin Well I don't know why the em100 doesn't work, but apparently it never did. Anyway the image seems to jump into ATF first, then to U-Boot SPL. So perhaps the problem is in ATF. From what I can tell, it prints about 10 characters of junk before it starts setting up SDRAM. Perhaps it has a clock wrong. In any case, it should be possible to jump directly into U-Boot SPL and hopefully the debug UART works. Can you try that, perhaps by building an image without ATF? Regards, SImon
On Mon, Aug 03, 2020 at 08:13:38PM -0600, Simon Glass wrote: > Hi Marty, > > On Mon, 3 Aug 2020 at 07:49, Simon Glass <sjg@chromium.org> wrote: > > > > Hi Marty, > > > > On Sun, 2 Aug 2020 at 21:02, Simon Glass <sjg@chromium.org> wrote: > > > > > > Hi Marty, > > > > > > > > > I dug this out but I cannot get it to boot with the em100 emulator. > > > I'll see if I can figure that out at some point. Sometimes I get > > > serial garbage as well. > > > > > > It is surprising that the flash is 8MB when Gru is 4MB. Must have run > > > out of room. > > > > Also I pushed the tree with your changes and one of mine here: > > > > https://github.com/sjg20/u-boot/tree/kevin > > Well I don't know why the em100 doesn't work, but apparently it never did. > > Anyway the image seems to jump into ATF first, then to U-Boot SPL. So > perhaps the problem is in ATF. From what I can tell, it prints about > 10 characters of junk before it starts setting up SDRAM. Perhaps it > has a clock wrong. > > In any case, it should be possible to jump directly into U-Boot SPL > and hopefully the debug UART works. Can you try that, perhaps by > building an image without ATF? > Sure, though I'm not certain how that even works, I don't recall explicitly setting that up. Just to put goals out there, my plan is to falcon-mode load a kernel and petitboot for use with 'normal' distros. > Regards, > SImon
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cee10f533f..0e3e1cc553 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -122,6 +122,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-gru-kevin.dtb \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h index 87cf351bab..331458c0e7 100644 --- a/include/dt-bindings/input/linux-event-codes.h +++ b/include/dt-bindings/input/linux-event-codes.h @@ -749,7 +749,8 @@ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ -#define SW_MAX 0x0f +#define SW_PEN_INSERTED 0x0f /* set = pen inserted */ +#define SW_MAX 0x10 #define SW_CNT (SW_MAX+1) /*