diff mbox series

[v14,12/20] riscv: Clear pending interrupts before enabling IPIs

Message ID 20200624104125.363509-13-seanga2@gmail.com
State Accepted
Delegated to: Andes
Headers show
Series riscv: Add Sipeed Maix support | expand

Commit Message

Sean Anderson June 24, 2020, 10:41 a.m. UTC
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>

Changes in v7:
- Split of into its own patch

 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)
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diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5f1c220e0c..f408e41ab9 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,6 +65,8 @@  _start:
 	li	t0, SIE_SSIE
+	/* Clear any pending IPIs */
+	csrc	MODE_PREFIX(ip), t0
 	csrs	MODE_PREFIX(ie), t0