| Message ID | 20190619122734.10948-4-lukma@denx.de |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show |
| Series | DM: Convert i.MX28 gpio, pinmux, spi and eth drivers to DM/DTS | expand |
On 6/19/19 2:27 PM, Lukasz Majewski wrote: > Those properties are U-Boot specific as the mxs gpio Linux driver (up to > version v5.1.11) is not supporting them. > > Signed-off-by: Lukasz Majewski <lukma@denx.de> [...] > +&gpio4 { > + gpio-ranges = <&pinctrl 120 0 21>; Are you sure the GPIO controller offset is 120 here ? Shouldn't that be 0 , while the pin controller offset should be 120 ? Some for the others ? > +}; >
Hi Marek, > On 6/19/19 2:27 PM, Lukasz Majewski wrote: > > Those properties are U-Boot specific as the mxs gpio Linux driver > > (up to version v5.1.11) is not supporting them. > > > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > > [...] > > > +&gpio4 { > > + gpio-ranges = <&pinctrl 120 0 21>; > > Are you sure the GPIO controller offset is 120 here ? Shouldn't that > be 0 , while the pin controller offset should be 120 ? Some for the > others ? Please find following excerpt from the documentation [1]: The format is: <[pin controller phandle], [GPIO controller offset], [pin controller offset], [number of pins]>; Example: gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; This means: - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 The 120 is the GPIO controller offset (logical one) [*] and corresponds to the final GPIO number. Then we do have the "pin controller offset" which is the pin number start index per controller (like gpio0, gpio1, gpioN). In my case it is always 0. The last entry - "number of pins" is the field which states the number of GPIO pins used from one particular controller (as I do use all of them per controller to map to GPIO [*]). This one is crucial for mxs_gpio as it fills the uc_priv->gpio_count (per controller). Note: [*] - i.MX28 doesn't have fixed number of pins per controller (contrary to e.g. i.MX6Q). It may have 29, 30, 32, etc. pins. > > > +}; > > > > Note: [1] - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/gpio/gpio.txt#L239 Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On 6/19/19 4:19 PM, Lukasz Majewski wrote: > Hi Marek, > >> On 6/19/19 2:27 PM, Lukasz Majewski wrote: >>> Those properties are U-Boot specific as the mxs gpio Linux driver >>> (up to version v5.1.11) is not supporting them. >>> >>> Signed-off-by: Lukasz Majewski <lukma@denx.de> >> >> [...] >> >>> +&gpio4 { >>> + gpio-ranges = <&pinctrl 120 0 21>; >> >> Are you sure the GPIO controller offset is 120 here ? Shouldn't that >> be 0 , while the pin controller offset should be 120 ? Some for the >> others ? > > Please find following excerpt from the documentation [1]: > > The format is: <[pin controller phandle], [GPIO controller offset], > [pin controller offset], [number of pins]>; > > Example: > > gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; > > This means: > - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and > - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 > > > The 120 is the GPIO controller offset (logical one) [*] and corresponds > to the final GPIO number. > > Then we do have the "pin controller offset" which is the pin number > start index per controller (like gpio0, gpio1, gpioN). In my case it is > always 0. I think you have these two swapped. The pin controller is the super-node here, hence each GPIO block is at offset N in the pin controller pin space. Each GPIO block then has GPIOs, which either start from 0 or M within the GPIO block pin space (in MXS case, this is always 0). [...]
On Wed, 19 Jun 2019 16:32:57 +0200 Marek Vasut <marex@denx.de> wrote: > On 6/19/19 4:19 PM, Lukasz Majewski wrote: > > Hi Marek, > > > >> On 6/19/19 2:27 PM, Lukasz Majewski wrote: > >>> Those properties are U-Boot specific as the mxs gpio Linux driver > >>> (up to version v5.1.11) is not supporting them. > >>> > >>> Signed-off-by: Lukasz Majewski <lukma@denx.de> > >> > >> [...] > >> > >>> +&gpio4 { > >>> + gpio-ranges = <&pinctrl 120 0 21>; > >> > >> Are you sure the GPIO controller offset is 120 here ? Shouldn't > >> that be 0 , while the pin controller offset should be 120 ? Some > >> for the others ? > > > > Please find following excerpt from the documentation [1]: > > > > The format is: <[pin controller phandle], [GPIO controller offset], > > [pin controller offset], [number of pins]>; > > > > Example: > > > > gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; > > > > This means: > > - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 > > and > > - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 > > > > > > The 120 is the GPIO controller offset (logical one) [*] and > > corresponds to the final GPIO number. > > > > Then we do have the "pin controller offset" which is the pin number > > start index per controller (like gpio0, gpio1, gpioN). In my case > > it is always 0. > > I think you have these two swapped. The pin controller is the > super-node here, hence each GPIO block is at offset N in the pin > controller pin space. Each GPIO block then has GPIOs, which either > start from 0 or M within the GPIO block pin space (in MXS case, this > is always 0). Yes, correct. This shall be <&pinctrl 0 120 21> I will prepare v6. > > [...] > > Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On 6/19/19 4:53 PM, Lukasz Majewski wrote: > On Wed, 19 Jun 2019 16:32:57 +0200 > Marek Vasut <marex@denx.de> wrote: > >> On 6/19/19 4:19 PM, Lukasz Majewski wrote: >>> Hi Marek, >>> >>>> On 6/19/19 2:27 PM, Lukasz Majewski wrote: >>>>> Those properties are U-Boot specific as the mxs gpio Linux driver >>>>> (up to version v5.1.11) is not supporting them. >>>>> >>>>> Signed-off-by: Lukasz Majewski <lukma@denx.de> >>>> >>>> [...] >>>> >>>>> +&gpio4 { >>>>> + gpio-ranges = <&pinctrl 120 0 21>; >>>> >>>> Are you sure the GPIO controller offset is 120 here ? Shouldn't >>>> that be 0 , while the pin controller offset should be 120 ? Some >>>> for the others ? >>> >>> Please find following excerpt from the documentation [1]: >>> >>> The format is: <[pin controller phandle], [GPIO controller offset], >>> [pin controller offset], [number of pins]>; >>> >>> Example: >>> >>> gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; >>> >>> This means: >>> - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 >>> and >>> - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 >>> >>> >>> The 120 is the GPIO controller offset (logical one) [*] and >>> corresponds to the final GPIO number. >>> >>> Then we do have the "pin controller offset" which is the pin number >>> start index per controller (like gpio0, gpio1, gpioN). In my case >>> it is always 0. >> >> I think you have these two swapped. The pin controller is the >> super-node here, hence each GPIO block is at offset N in the pin >> controller pin space. Each GPIO block then has GPIOs, which either >> start from 0 or M within the GPIO block pin space (in MXS case, this >> is always 0). > > Yes, correct. This shall be <&pinctrl 0 120 21> > > I will prepare v6. And update the GPIO controller driver accordingly.
On Wed, 19 Jun 2019 17:05:15 +0200 Marek Vasut <marex@denx.de> wrote: > On 6/19/19 4:53 PM, Lukasz Majewski wrote: > > On Wed, 19 Jun 2019 16:32:57 +0200 > > Marek Vasut <marex@denx.de> wrote: > > > >> On 6/19/19 4:19 PM, Lukasz Majewski wrote: > >>> Hi Marek, > >>> > >>>> On 6/19/19 2:27 PM, Lukasz Majewski wrote: > >>>>> Those properties are U-Boot specific as the mxs gpio Linux > >>>>> driver (up to version v5.1.11) is not supporting them. > >>>>> > >>>>> Signed-off-by: Lukasz Majewski <lukma@denx.de> > >>>> > >>>> [...] > >>>> > >>>>> +&gpio4 { > >>>>> + gpio-ranges = <&pinctrl 120 0 21>; > >>>> > >>>> Are you sure the GPIO controller offset is 120 here ? Shouldn't > >>>> that be 0 , while the pin controller offset should be 120 ? Some > >>>> for the others ? > >>> > >>> Please find following excerpt from the documentation [1]: > >>> > >>> The format is: <[pin controller phandle], [GPIO controller > >>> offset], [pin controller offset], [number of pins]>; > >>> > >>> Example: > >>> > >>> gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; > >>> > >>> This means: > >>> - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 > >>> and > >>> - pins 50..69 on pin controller "bar" is mapped to GPIO line > >>> 10..29 > >>> > >>> > >>> The 120 is the GPIO controller offset (logical one) [*] and > >>> corresponds to the final GPIO number. > >>> > >>> Then we do have the "pin controller offset" which is the pin > >>> number start index per controller (like gpio0, gpio1, gpioN). In > >>> my case it is always 0. > >> > >> I think you have these two swapped. The pin controller is the > >> super-node here, hence each GPIO block is at offset N in the pin > >> controller pin space. Each GPIO block then has GPIOs, which either > >> start from 0 or M within the GPIO block pin space (in MXS case, > >> this is always 0). > > > > Yes, correct. This shall be <&pinctrl 0 120 21> > > > > I will prepare v6. > > And update the GPIO controller driver accordingly. > Only the DTS file needs update as I'm not using those particular entries for setting up the DM gpio controller. The driver code doesn't need update. Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
diff --git a/arch/arm/dts/imx28-u-boot.dtsi b/arch/arm/dts/imx28-u-boot.dtsi new file mode 100644 index 0000000000..a5bf74b1b7 --- /dev/null +++ b/arch/arm/dts/imx28-u-boot.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ +#include "imx28.dtsi" + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 29>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 29 0 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 61 0 28>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 89 0 31>; +}; + +&gpio4 { + gpio-ranges = <&pinctrl 120 0 21>; +};
Those properties are U-Boot specific as the mxs gpio Linux driver (up to version v5.1.11) is not supporting them. Signed-off-by: Lukasz Majewski <lukma@denx.de> --- Changes in v5: - Use "ARM: dts: imx: tags" Changes in v4: - New file - imx28-u-boot.dtsi Changes in v3: None Changes in v2: None arch/arm/dts/imx28-u-boot.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/arm/dts/imx28-u-boot.dtsi