| Message ID | 20181122044503.18334-1-anup@brainfault.org |
|---|---|
| State | Not Applicable |
| Headers | show |
Hi All, Is it possible to include this series for next U-Boot release? Regards, Anup
> > Subject: [PATCH v4 0/3] RISC-V S-mode support > > > > This patchset allows us runing u-boot in S-mode which is useful on platforms > > where M-mode runtime firmware is an independent firmware and u-boot is used > > as last stage OS bootloader. > > > > The patchset based upon git://git.denx.de/u-boot-riscv.git Hi Anup I apply your patch-sets fail on u-boot-riscv.git Can you tell me which commit id I shall base on ? Rick > > and is tested on QEMU in both M-mode and S-mode. > > > > For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit > > 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) > > applied with following changes: > > > > diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 > > 100644 > > --- a/machine/emulation.c > > +++ b/machine/emulation.c > > @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t > > mstatus, uintptr_t* result > > > > switch (num) > > { > > + case CSR_MISA: > > + *result = read_csr(misa); > > + return 0; > > + case CSR_MHARTID: > > + *result = read_csr(mhartid); > > + return 0; > > case CSR_CYCLE: > > if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) > > return -1; > > > > Changes since v3: > > - Replaced 'u-boot' with 'U-Boot' in commit message > > - Dropped 'an' in RISCV_SMODE kconfig option help message > > - Added appropriate #ifdef in arch/riscv/lib/interrupts.c > > > > Changes since v2: > > - Dropped 'default n" from RISCV_SMODE kconfig option > > - Replaced '-smode_' in defconfig names with '_smode_' > > > > Changes since v1: > > - Rebased upon latest git://git.denx.de/u-boot-riscv.git > > - Add details in cover letter for running u-boot in S-mode > > using BBL > > > > Anup Patel (3): > > riscv: Add kconfig option to run U-Boot in S-mode > > riscv: qemu: Use different SYS_TEXT_BASE for S-mode > > riscv: Add S-mode defconfigs for QEMU virt machine > > > > arch/riscv/Kconfig | 5 ++++ > > arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++ > > arch/riscv/include/asm/encoding.h | 2 ++ > > arch/riscv/lib/interrupts.c | 36 +++++++++++++++++++------- > > board/emulation/qemu-riscv/Kconfig | 3 ++- > > board/emulation/qemu-riscv/MAINTAINERS | 2 ++ > > configs/qemu-riscv32_smode_defconfig | 10 +++++++ > > configs/qemu-riscv64_smode_defconfig | 11 ++++++++ > > 8 files changed, 92 insertions(+), 10 deletions(-) create mode 100644 > > configs/qemu-riscv32_smode_defconfig > > create mode 100644 configs/qemu-riscv64_smode_defconfig > > > > -- > > 2.17.1 >
> Hi All, > > > > Is it possible to include this series for next U-Boot release? Hi Anup Yes. I will do some verification. And prepare the PR ASAP. Can you prepare a version which will be rebase on the latest u-boot-riscv.git Thanks Rick > > > > Regards, > > Anup >
On Mon, Nov 26, 2018 at 2:06 PM Rick Chen <rickchen36@gmail.com> wrote: > > > Hi All, > > > > > > > > Is it possible to include this series for next U-Boot release? > > Hi Anup > > Yes. > > I will do some verification. > And prepare the PR ASAP. > > Can you prepare a version which will be rebase on the latest u-boot-riscv.git Sure, give me few minutes. I will send v5 based on: commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb riscv: cache: Implement i/dcache [status, enable, disable] Regards, Anup
diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;