| Message ID | 20180929234553.31019-5-vagrant@debian.org |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | [U-Boot,1/5] mmc: sunxi: add support for automatic delay calibration | expand |
Hi, On Sat, Sep 29, 2018 at 04:45:52PM -0700, Vagrant Cascadian wrote: > From: Vasily Khoruzhick <anarsoul@gmail.com> > > Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has > two groups of pinmuxes on PL bank, so it's called R_I2C. > > Add support for this I2C controller and the pinmux which doesn't conflict > with RSB > > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> > Signed-off-by: Vagrant Cascadian <vagrant@debian.org> > --- > > arch/arm/dts/sun50i-a64.dtsi | 17 +++++++++++++++++ > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > arch/arm/mach-sunxi/Kconfig | 1 + > board/sunxi/board.c | 6 ++++++ > 4 files changed, 25 insertions(+) > > diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi > index 7a083637c4..80ddcf0af3 100644 > --- a/arch/arm/dts/sun50i-a64.dtsi > +++ b/arch/arm/dts/sun50i-a64.dtsi > @@ -627,6 +627,18 @@ > }; > }; > > + r_i2c: i2c@1f02400 { > + compatible = "allwinner,sun50i-a64-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01f02400 0x400>; > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&r_ccu 9>; > + resets = <&r_ccu 5>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > gic: interrupt-controller@1c81000 { > compatible = "arm,gic-400"; > reg = <0x01c81000 0x1000>, > @@ -679,6 +691,11 @@ > pins = "PL0", "PL1"; > function = "s_rsb"; > }; > + > + r_i2c_pins_a: i2c-a { > + pins = "PL8", "PL9"; > + function = "s_i2c"; > + }; These changes are in the Linux DT, so we'd be better off syncing that DT, instead of adding just those two nodes. Thanks! Maxime
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..80ddcf0af3 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -627,6 +627,18 @@ }; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 9>; + resets = <&r_ccu 5>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, @@ -679,6 +691,11 @@ pins = "PL0", "PL1"; function = "s_rsb"; }; + + r_i2c_pins_a: i2c-a { + pins = "PL8", "PL9"; + function = "s_i2c"; + }; }; r_rsb: rsb@1f03400 { diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 6a5eafc3d3..2daf23f6f5 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -211,6 +211,7 @@ enum sunxi_gpio_number { #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2 #define SUN9I_GPN_R_RSB 3 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ae77ee9e8e..fccef9d706 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -273,6 +273,7 @@ config MACH_SUN50I select DM_I2C select MMC_SUNXI_SUPPORTS_CALIBRATION select PHY_SUN4I_USB + select SUN6I_PRCM select SUNXI_DE2 select SUNXI_GEN_SUN6I select SUPPORT_SPL diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d1d7f9f400..90f8bc0a6e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -168,10 +168,16 @@ void i2c_init_board(void) #endif #ifdef CONFIG_R_I2C_ENABLE +#ifdef CONFIG_MACH_SUN50I + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif +#endif } #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)