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[U-Boot,v2,1/6] sunxi: map DRAM part with 3G size on AArch64

Message ID 20180323081857.57138-2-icenowy@aosc.io
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series Add 3GiB DRAM support to 64-bit Allwinner SoCs | expand

Commit Message

Icenowy Zheng March 23, 2018, 8:18 a.m. UTC 
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
No changes in v2.

 arch/arm/mach-sunxi/board.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 1753faec1d..89696e0890 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -53,7 +53,7 @@  static struct mm_region sunxi_mem_map[] = {
 		/* RAM */
 		.virt = 0x40000000UL,
 		.phys = 0x40000000UL,
-		.size = 0x80000000UL,
+		.size = 0xC0000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {